pub trait GpioIdrIdr5<T: GpioPortMap>: GpioIdr<T> {
type UGpioIdrIdr5: RegField<Urt, Reg = Self::UGpioIdr, URegField = Self::UGpioIdrIdr5, SRegField = Self::SGpioIdrIdr5, CRegField = Self::CGpioIdrIdr5> + URoRoRegFieldBit;
type SGpioIdrIdr5: RegField<Srt, Reg = Self::SGpioIdr, URegField = Self::UGpioIdrIdr5, SRegField = Self::SGpioIdrIdr5, CRegField = Self::CGpioIdrIdr5> + SRoRoRegFieldBit;
type CGpioIdrIdr5: RegField<Crt, Reg = Self::CGpioIdr, URegField = Self::UGpioIdrIdr5, SRegField = Self::SGpioIdrIdr5, CRegField = Self::CGpioIdrIdr5> + CRoRoRegFieldBit;
}