[−][src]Trait drone_stm32_map_periph_gpio::GpioAfrlAfrl5

pub trait GpioAfrlAfrl5<T: GpioPortMap>: GpioAfrl<T> {
    type UGpioAfrlAfrl5: RegField<Urt, Reg = Self::UGpioAfrl, URegField = Self::UGpioAfrlAfrl5, SRegField = Self::SGpioAfrlAfrl5, CRegField = Self::CGpioAfrlAfrl5> + URwRwRegFieldBits;
    type SGpioAfrlAfrl5: RegField<Srt, Reg = Self::SGpioAfrl, URegField = Self::UGpioAfrlAfrl5, SRegField = Self::SGpioAfrlAfrl5, CRegField = Self::CGpioAfrlAfrl5> + SRwRwRegFieldBits;
    type CGpioAfrlAfrl5: RegField<Crt, Reg = Self::CGpioAfrl, URegField = Self::UGpioAfrlAfrl5, SRegField = Self::SGpioAfrlAfrl5, CRegField = Self::CGpioAfrlAfrl5> + CRwRwRegFieldBits;
}

Associated Types

`type UGpioAfrlAfrl5: RegField<Urt, Reg = Self::UGpioAfrl, URegField = Self::UGpioAfrlAfrl5, SRegField = Self::SGpioAfrlAfrl5, CRegField = Self::CGpioAfrlAfrl5> + URwRwRegFieldBits`

`type SGpioAfrlAfrl5: RegField<Srt, Reg = Self::SGpioAfrl, URegField = Self::UGpioAfrlAfrl5, SRegField = Self::SGpioAfrlAfrl5, CRegField = Self::CGpioAfrlAfrl5> + SRwRwRegFieldBits`

`type CGpioAfrlAfrl5: RegField<Crt, Reg = Self::CGpioAfrl, URegField = Self::UGpioAfrlAfrl5, SRegField = Self::SGpioAfrlAfrl5, CRegField = Self::CGpioAfrlAfrl5> + CRwRwRegFieldBits`

Loading content...

Implementors

`impl GpioAfrlAfrl5<GpioA> for GpioA`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioB> for GpioB`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioC> for GpioC`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioD> for GpioD`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioE> for GpioE`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioF> for GpioF`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioG> for GpioG`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioH> for GpioH`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

`impl GpioAfrlAfrl5<GpioI> for GpioI`[src]

`type UGpioAfrlAfrl5 = Afrl5<Urt>`

`type SGpioAfrlAfrl5 = Afrl5<Srt>`

`type CGpioAfrlAfrl5 = Afrl5<Crt>`

Loading content...