[−][src]Trait drone_stm32_map_periph_gpio::pin::GpioIdr

pub trait GpioIdr {
    type GpioIdrVal: Bitfield<Bits = u32>;
    type UGpioIdr: Reg<Urt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + URoReg;
    type SGpioIdr: Reg<Srt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + SRoReg;
    type CGpioIdr: Reg<Crt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + CRoReg;
}

Associated Types

`type GpioIdrVal: Bitfield<Bits = u32>`

`type UGpioIdr: Reg<Urt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + URoReg`

`type SGpioIdr: Reg<Srt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + SRoReg`

`type CGpioIdr: Reg<Crt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + CRoReg`

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Implementors

`impl GpioIdr for GpioA0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioB9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioC9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioD9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioE9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioF9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioG9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioH9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioI9`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

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[−][src]Trait drone_stm32_map_periph_gpio::pin::GpioIdr

Associated Types

type GpioIdrVal: Bitfield<Bits = u32>

type UGpioIdr: Reg<Urt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + URoReg

type SGpioIdr: Reg<Srt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + SRoReg

type CGpioIdr: Reg<Crt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + CRoReg

Implementors

impl GpioIdr for GpioA0[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA1[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA10[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA11[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA12[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA13[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA14[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA15[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA2[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA3[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA4[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA5[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA6[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA7[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

type SGpioIdr = Reg<Srt>

type CGpioIdr = Reg<Crt>

impl GpioIdr for GpioA8[src]

type GpioIdrVal = Val

type UGpioIdr = Reg<Urt>

`type GpioIdrVal: Bitfield<Bits = u32>`

`type UGpioIdr: Reg<Urt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + URoReg`

`type SGpioIdr: Reg<Srt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + SRoReg`

`type CGpioIdr: Reg<Crt, Val = Self::GpioIdrVal, UReg = Self::UGpioIdr, SReg = Self::SGpioIdr, CReg = Self::CGpioIdr> + CRoReg`

`impl GpioIdr for GpioA0`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA1`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA10`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA11`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA12`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA13`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA14`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA15`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA2`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA3`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA4`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA5`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA6`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA7`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA8`[src]

`type GpioIdrVal = Val`

`type UGpioIdr = Reg<Urt>`

`type SGpioIdr = Reg<Srt>`

`type CGpioIdr = Reg<Crt>`

`impl GpioIdr for GpioA9`[src]