[−][src]Trait drone_stm32_map_periph_gpio::pin::GpioAfr

pub trait GpioAfr {
    type GpioAfrVal: Bitfield<Bits = u32>;
    type UGpioAfr: Reg<Urt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + URwReg;
    type SGpioAfr: Reg<Srt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + SRwReg;
    type CGpioAfr: Reg<Crt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + CRwReg;
}

Associated Types

`type GpioAfrVal: Bitfield<Bits = u32>`

`type UGpioAfr: Reg<Urt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + URwReg`

`type SGpioAfr: Reg<Srt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + SRwReg`

`type CGpioAfr: Reg<Crt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + CRwReg`

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Implementors

`impl GpioAfr for GpioA0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioB9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioC9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioD9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioE9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioF9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioG9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioH9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioI9`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

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[−][src]Trait drone_stm32_map_periph_gpio::pin::GpioAfr

Associated Types

type GpioAfrVal: Bitfield<Bits = u32>

type UGpioAfr: Reg<Urt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + URwReg

type SGpioAfr: Reg<Srt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + SRwReg

type CGpioAfr: Reg<Crt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + CRwReg

Implementors

impl GpioAfr for GpioA0[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA1[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA10[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA11[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA12[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA13[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA14[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA15[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA2[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA3[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA4[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA5[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA6[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA7[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

type SGpioAfr = Reg<Srt>

type CGpioAfr = Reg<Crt>

impl GpioAfr for GpioA8[src]

type GpioAfrVal = Val

type UGpioAfr = Reg<Urt>

`type GpioAfrVal: Bitfield<Bits = u32>`

`type UGpioAfr: Reg<Urt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + URwReg`

`type SGpioAfr: Reg<Srt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + SRwReg`

`type CGpioAfr: Reg<Crt, Val = Self::GpioAfrVal, UReg = Self::UGpioAfr, SReg = Self::SGpioAfr, CReg = Self::CGpioAfr> + CRwReg`

`impl GpioAfr for GpioA0`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA1`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA10`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA11`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA12`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA13`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA14`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA15`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA2`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA3`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA4`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA5`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA6`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA7`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA8`[src]

`type GpioAfrVal = Val`

`type UGpioAfr = Reg<Urt>`

`type SGpioAfr = Reg<Srt>`

`type CGpioAfr = Reg<Crt>`

`impl GpioAfr for GpioA9`[src]