[−][src]Trait drone_stm32_map_periph_exti::ExtiSwier

pub trait ExtiSwier {
    type ExtiSwierVal: Bitfield<Bits = u32>;
    type UExtiSwier: Reg<Urt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + URwRegBitBand;
    type SExtiSwier: Reg<Srt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + SRwRegBitBand;
    type CExtiSwier: Reg<Crt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + CRwRegBitBand;
}

Associated Types

`type ExtiSwierVal: Bitfield<Bits = u32>`

`type UExtiSwier: Reg<Urt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + URwRegBitBand`

`type SExtiSwier: Reg<Srt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + SRwRegBitBand`

`type CExtiSwier: Reg<Crt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + CRwRegBitBand`

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Implementors

`impl ExtiSwier for Exti0`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti1`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti10`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti11`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti12`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti13`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti14`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti15`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti16`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti18`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti19`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti2`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti20`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti21`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti22`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti3`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti35`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti36`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti37`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti38`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti4`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti5`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti6`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti7`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti8`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti9`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

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[−][src]Trait drone_stm32_map_periph_exti::ExtiSwier

Associated Types

type ExtiSwierVal: Bitfield<Bits = u32>

type UExtiSwier: Reg<Urt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + URwRegBitBand

type SExtiSwier: Reg<Srt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + SRwRegBitBand

type CExtiSwier: Reg<Crt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + CRwRegBitBand

Implementors

impl ExtiSwier for Exti0[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti1[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti10[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti11[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti12[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti13[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti14[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti15[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti16[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti18[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti19[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti2[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti20[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti21[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

type SExtiSwier = Reg<Srt>

type CExtiSwier = Reg<Crt>

impl ExtiSwier for Exti22[src]

type ExtiSwierVal = Val

type UExtiSwier = Reg<Urt>

`type ExtiSwierVal: Bitfield<Bits = u32>`

`type UExtiSwier: Reg<Urt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + URwRegBitBand`

`type SExtiSwier: Reg<Srt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + SRwRegBitBand`

`type CExtiSwier: Reg<Crt, Val = Self::ExtiSwierVal, UReg = Self::UExtiSwier, SReg = Self::SExtiSwier, CReg = Self::CExtiSwier> + CRwRegBitBand`

`impl ExtiSwier for Exti0`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti1`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti10`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti11`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti12`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti13`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti14`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti15`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti16`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti18`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti19`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti2`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti20`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti21`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti22`[src]

`type ExtiSwierVal = Val`

`type UExtiSwier = Reg<Urt>`

`type SExtiSwier = Reg<Srt>`

`type CExtiSwier = Reg<Crt>`

`impl ExtiSwier for Exti3`[src]