[−][src]Trait drone_stm32_map_periph_exti::ExtiImr

pub trait ExtiImr {
    type ExtiImrVal: Bitfield<Bits = u32>;
    type UExtiImr: Reg<Urt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + URwRegBitBand;
    type SExtiImr: Reg<Srt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + SRwRegBitBand;
    type CExtiImr: Reg<Crt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + CRwRegBitBand;
}

Associated Types

`type ExtiImrVal: Bitfield<Bits = u32>`

`type UExtiImr: Reg<Urt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + URwRegBitBand`

`type SExtiImr: Reg<Srt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + SRwRegBitBand`

`type CExtiImr: Reg<Crt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + CRwRegBitBand`

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Implementors

`impl ExtiImr for Exti0`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti1`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti10`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti11`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti12`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti13`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti14`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti15`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti16`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti17`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti18`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti19`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti2`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti20`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti21`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti22`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti23`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti24`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti25`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti26`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti27`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti28`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti29`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti3`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti30`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti31`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti32`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti33`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti34`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti35`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti36`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti37`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti38`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti39`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti4`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti40`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti5`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti6`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti7`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti8`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti9`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

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[−][src]Trait drone_stm32_map_periph_exti::ExtiImr

Associated Types

type ExtiImrVal: Bitfield<Bits = u32>

type UExtiImr: Reg<Urt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + URwRegBitBand

type SExtiImr: Reg<Srt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + SRwRegBitBand

type CExtiImr: Reg<Crt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + CRwRegBitBand

Implementors

impl ExtiImr for Exti0[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti1[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti10[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti11[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti12[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti13[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti14[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti15[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti16[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti17[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti18[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti19[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti2[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti20[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

type SExtiImr = Reg<Srt>

type CExtiImr = Reg<Crt>

impl ExtiImr for Exti21[src]

type ExtiImrVal = Val

type UExtiImr = Reg<Urt>

`type ExtiImrVal: Bitfield<Bits = u32>`

`type UExtiImr: Reg<Urt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + URwRegBitBand`

`type SExtiImr: Reg<Srt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + SRwRegBitBand`

`type CExtiImr: Reg<Crt, Val = Self::ExtiImrVal, UReg = Self::UExtiImr, SReg = Self::SExtiImr, CReg = Self::CExtiImr> + CRwRegBitBand`

`impl ExtiImr for Exti0`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti1`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti10`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti11`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti12`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti13`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti14`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti15`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti16`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti17`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti18`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti19`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti2`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti20`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti21`[src]

`type ExtiImrVal = Val`

`type UExtiImr = Reg<Urt>`

`type SExtiImr = Reg<Srt>`

`type CExtiImr = Reg<Crt>`

`impl ExtiImr for Exti22`[src]