[−][src]Trait drone_stm32_map_periph_exti::ExtiEmr

pub trait ExtiEmr {
    type ExtiEmrVal: Bitfield<Bits = u32>;
    type UExtiEmr: Reg<Urt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + URwRegBitBand;
    type SExtiEmr: Reg<Srt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + SRwRegBitBand;
    type CExtiEmr: Reg<Crt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + CRwRegBitBand;
}

Associated Types

`type ExtiEmrVal: Bitfield<Bits = u32>`

`type UExtiEmr: Reg<Urt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + URwRegBitBand`

`type SExtiEmr: Reg<Srt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + SRwRegBitBand`

`type CExtiEmr: Reg<Crt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + CRwRegBitBand`

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Implementors

`impl ExtiEmr for Exti0`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti1`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti10`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti11`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti12`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti13`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti14`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti15`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti16`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti17`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti18`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti19`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti2`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti20`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti21`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti22`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti23`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti24`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti25`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti26`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti27`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti28`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti29`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti3`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti30`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti31`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti32`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti33`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti34`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti35`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti36`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti37`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti38`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti39`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti4`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti40`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti5`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti6`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti7`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti8`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti9`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

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[−][src]Trait drone_stm32_map_periph_exti::ExtiEmr

Associated Types

type ExtiEmrVal: Bitfield<Bits = u32>

type UExtiEmr: Reg<Urt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + URwRegBitBand

type SExtiEmr: Reg<Srt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + SRwRegBitBand

type CExtiEmr: Reg<Crt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + CRwRegBitBand

Implementors

impl ExtiEmr for Exti0[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti1[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti10[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti11[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti12[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti13[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti14[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti15[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti16[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti17[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti18[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti19[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti2[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti20[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

type SExtiEmr = Reg<Srt>

type CExtiEmr = Reg<Crt>

impl ExtiEmr for Exti21[src]

type ExtiEmrVal = Val

type UExtiEmr = Reg<Urt>

`type ExtiEmrVal: Bitfield<Bits = u32>`

`type UExtiEmr: Reg<Urt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + URwRegBitBand`

`type SExtiEmr: Reg<Srt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + SRwRegBitBand`

`type CExtiEmr: Reg<Crt, Val = Self::ExtiEmrVal, UReg = Self::UExtiEmr, SReg = Self::SExtiEmr, CReg = Self::CExtiEmr> + CRwRegBitBand`

`impl ExtiEmr for Exti0`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti1`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti10`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti11`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti12`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti13`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti14`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti15`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti16`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti17`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti18`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti19`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti2`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti20`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti21`[src]

`type ExtiEmrVal = Val`

`type UExtiEmr = Reg<Urt>`

`type SExtiEmr = Reg<Srt>`

`type CExtiEmr = Reg<Crt>`

`impl ExtiEmr for Exti22`[src]