type UAdcDifselDifsel1618: RegField<Urt, Reg = Self::UAdcDifsel, URegField = Self::UAdcDifselDifsel1618, SRegField = Self::SAdcDifselDifsel1618, CRegField = Self::CAdcDifselDifsel1618> + URoRwRegFieldBits
type SAdcDifselDifsel1618: RegField<Srt, Reg = Self::SAdcDifsel, URegField = Self::UAdcDifselDifsel1618, SRegField = Self::SAdcDifselDifsel1618, CRegField = Self::CAdcDifselDifsel1618> + SRoRwRegFieldBits
type CAdcDifselDifsel1618: RegField<Crt, Reg = Self::CAdcDifsel, URegField = Self::UAdcDifselDifsel1618, SRegField = Self::SAdcDifselDifsel1618, CRegField = Self::CAdcDifselDifsel1618> + CRoRwRegFieldBits
impl AdcDifselDifsel1618<Adc1> for Adc1
[src]type UAdcDifselDifsel1618 = Difsel1618<Urt>
type SAdcDifselDifsel1618 = Difsel1618<Srt>
type CAdcDifselDifsel1618 = Difsel1618<Crt>