type UAdcDifselDifsel115: RegField<Urt, Reg = Self::UAdcDifsel, URegField = Self::UAdcDifselDifsel115, SRegField = Self::SAdcDifselDifsel115, CRegField = Self::CAdcDifselDifsel115> + URwRwRegFieldBits
type SAdcDifselDifsel115: RegField<Srt, Reg = Self::SAdcDifsel, URegField = Self::UAdcDifselDifsel115, SRegField = Self::SAdcDifselDifsel115, CRegField = Self::CAdcDifselDifsel115> + SRwRwRegFieldBits
type CAdcDifselDifsel115: RegField<Crt, Reg = Self::CAdcDifsel, URegField = Self::UAdcDifselDifsel115, SRegField = Self::SAdcDifselDifsel115, CRegField = Self::CAdcDifselDifsel115> + CRwRwRegFieldBits
impl AdcDifselDifsel115<Adc1> for Adc1
[src]type UAdcDifselDifsel115 = Difsel115<Urt>
type SAdcDifselDifsel115 = Difsel115<Srt>
type CAdcDifselDifsel115 = Difsel115<Crt>