Module drone_cortexm::map::reg::scb::demcr

Debug Exception and Monitor Control Register.

Structs

Hold	Debug Exception and Monitor Control Register.
MonEn	Enable the DebugMonitor exception.
MonPend	Sets or clears the pending state of the DebugMonitor exception.
MonReq	DebugMonitor semaphore bit.
MonStep	Setting this bit to 1 makes the step request pending.
Reg	Debug Exception and Monitor Control Register.
Trcena	Global enable for all DWT and ITM features.
Val	Debug Exception and Monitor Control Register.
VcBuserr	Enable halting debug trap on a BusFault exception.
VcChkerr	Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error.
VcCorereset	Enable Reset Vector Catch. This causes a Local reset to halt a running system.
VcHarderr	Enable halting debug trap on a HardFault exception.
VcInterr	Enable halting debug trap on a fault occurring during exception entry or exception return.
VcMmerr	Enable halting debug trap on a MemManage exception.
VcNocperr	Enable halting debug trap on a UsageFault caused by an access to a Coprocessor.
VcStaterr	Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception.