1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
#![cfg_attr(feature = "std", allow(unreachable_code, unused_variables))]
mod port;
pub use self::port::Port;
use crate::{
map::reg::{dwt, itm, tpiu},
processor,
reg::prelude::*,
};
use core::ptr::read_volatile;
use drone_core::token::Token;
pub const PORTS_COUNT: u8 = 32;
const ITM_TER: usize = 0xE000_0E00;
const ITM_TCR: usize = 0xE000_0E80;
#[inline]
pub fn is_enabled() -> bool {
#[cfg(feature = "std")]
return unimplemented!();
unsafe { read_volatile(ITM_TCR as *const u32) & 1 != 0 }
}
#[inline]
pub fn is_port_enabled(port: usize) -> bool {
#[cfg(feature = "std")]
return unimplemented!();
unsafe { read_volatile(ITM_TER as *const u32) & 1 << port != 0 }
}
#[inline(always)]
pub fn flush() {
#[inline(never)]
fn flush() {
let tcr = unsafe { itm::Tcr::<Urt>::take() };
while tcr.load().busy() {}
let acpr = unsafe { tpiu::Acpr::<Urt>::take() };
processor::spin(acpr.load().swoscaler() * 64);
}
if is_enabled() {
flush();
}
}
#[inline]
pub fn sync() {
#[cfg(feature = "std")]
return unimplemented!();
let mut cyccnt = unsafe { dwt::Cyccnt::<Urt>::take() };
cyccnt.store(|r| r.write_cyccnt(0xFFFF_FFFF));
}
#[inline]
pub fn update_prescaler(swoscaler: u32) {
#[cfg(feature = "std")]
return unimplemented!();
let mut acpr = unsafe { tpiu::Acpr::<Urt>::take() };
acpr.store(|r| r.write_swoscaler(swoscaler));
sync();
}
#[doc(hidden)]
#[macro_export]
macro_rules! swo_set_log {
() => {
const _: () = {
$crate::reg::assert_taken!("dwt_cyccnt");
$crate::reg::assert_taken!("itm_tpr");
$crate::reg::assert_taken!("itm_tcr");
$crate::reg::assert_taken!("itm_lar");
$crate::reg::assert_taken!("tpiu_acpr");
$crate::reg::assert_taken!("tpiu_sppr");
$crate::reg::assert_taken!("tpiu_ffcr");
#[no_mangle]
extern "C" fn drone_log_is_enabled(port: u8) -> bool {
$crate::swo::is_port_enabled(port as usize)
}
#[no_mangle]
extern "C" fn drone_log_write_bytes(port: u8, buffer: *const u8, count: usize) {
let bytes = unsafe { ::core::slice::from_raw_parts(buffer, count) };
$crate::swo::Port::new(port).write_bytes(bytes);
}
#[no_mangle]
extern "C" fn drone_log_write_u8(port: u8, value: u8) {
$crate::swo::Port::new(port).write(value);
}
#[no_mangle]
extern "C" fn drone_log_write_u16(port: u8, value: u16) {
$crate::swo::Port::new(port).write(value);
}
#[no_mangle]
extern "C" fn drone_log_write_u32(port: u8, value: u32) {
$crate::swo::Port::new(port).write(value);
}
#[no_mangle]
extern "C" fn drone_log_flush() {
$crate::swo::flush();
}
};
};
}
#[doc(inline)]
pub use crate::swo_set_log as set_log;