[−][src]Macro drone_stm32_map_periph_uart::periph_lpuart1
macro_rules! periph_lpuart1 { periph::map! { #[doc = $uart_macro_doc] pub macro $uart_macro; #[doc = $uart_ty_doc] pub struct $uart_ty; impl UartMap for $uart_ty {} drone_stm32_map_pieces::reg; crate; RCC { BUSENR { $busenr Shared; UARTEN { $uarten } } BUSRSTR { $busrstr Shared; UARTRST { $uartrst } } BUSSMENR { $bussmenr Shared; UARTSMEN { $uartsmen } } CCIPR { CCIPR Shared; UARTSEL { $uartsel } } } UART { $uart; CR1 { CR1; CMIE { CMIE } DEAT0 { DEAT0 } DEAT1 { DEAT1 } DEAT2 { DEAT2 } DEAT3 { DEAT3 } DEAT4 { DEAT4 } DEDT0 { DEDT0 } DEDT1 { DEDT1 } DEDT2 { DEDT2 } DEDT3 { DEDT3 } DEDT4 { DEDT4 } EOBIE { $($eobie Option)* } IDLEIE { IDLEIE } M0 { M0 } M1 { M1 } MME { MME } OVER8 { $($over8 Option)* } PCE { PCE } PEIE { PEIE } PS { PS } RE { RE } RTOIE { $($rtoie Option)* } RXNEIE { RXNEIE } TCIE { TCIE } TE { TE } TXEIE { TXEIE } UESM { UESM } UE { UE } WAKE { WAKE } } CR2 { CR2; ABREN { $($abren Option)* } ABRMOD0 { $($abrmod0 Option)* } ABRMOD1 { $($abrmod1 Option)* } ADD0_3 { ADD0_3 } ADD4_7 { ADD4_7 } ADDM7 { ADDM7 } CLKEN { CLKEN } CPHA { $($cpha Option)* } CPOL { $($cpol Option)* } LBCL { $($lbcl Option)* } LBDIE { $($lbdie Option)* } LBDL { $($lbdl Option)* } LINEN { $($linen Option)* } MSBFIRST { MSBFIRST } RTOEN { $($rtoen Option)* } RXINV { RXINV } STOP { STOP } SWAP { SWAP } TAINV { TAINV } TXINV { TXINV } } CR3 { CR3; CTSE { CTSE } CTSIE { CTSIE } DDRE { DDRE } DEM { DEM } DEP { DEP } DMAR { DMAR } DMAT { DMAT } EIE { EIE } HDSEL { HDSEL } IREN { $($iren Option)* } IRLP { $($irlp Option)* } NACK { $($nack Option)* } ONEBIT { $($onebit Option)* } OVRDIS { OVRDIS } RTSE { RTSE } SCARCNT { $($scarcnt Option)* } SCEN { $($scen Option)* } #[cfg(any( feature = "stm32l4x1", feature = "stm32l4x2", ))] TCBGTIE { $($tcbgtie Option)* } #[cfg(any( feature = "stm32l4x1", feature = "stm32l4x2", ))] UCESM { UCESM } WUFIE { WUFIE } WUS { WUS } } BRR { BRR; BRR { $($brr Option)* } DIV_Fraction { $($div_fraction Option)* } DIV_Mantissa { $($div_mantissa Option)* } } GTPR { $( $gtpr Option; GT { GT } PSC { PSC } )* } RTOR { $( $rtor Option; BLEN { BLEN } RTO { RTO } )* } RQR { RQR; ABRRQ { $($abrrq Option)* } MMRQ { MMRQ } RXFRQ { RXFRQ } SBKRQ { SBKRQ } TXFRQ { $($txfrq Option)* } } ISR { ISR; REACK { REACK } TEACK { TEACK } WUF { WUF } RWU { RWU } SBKF { SBKF } CMF { CMF } BUSY { BUSY } ABRF { $($abrf Option)* } ABRE { $($abre Option)* } EOBF { $($eobf Option)* } RTOF { $($rtof Option)* } CTS { CTS } CTSIF { CTSIF } LBDF { $($lbdf Option)* } TXE { TXE } TC { TC } #[cfg(any( feature = "stm32l4x1", feature = "stm32l4x2", ))] TCBGT { $($tcbgt Option)* } RXNE { RXNE } IDLE { IDLE } ORE { ORE } NF { NF } FE { FE } PE { PE } } ICR { ICR; WUCF { WUCF } CMCF { CMCF } EOBCF { $($eobcf Option)* } RTOCF { $($rtocf Option)* } CTSCF { CTSCF } LBDCF { $($lbdcf Option)* } TCCF { TCCF } IDLECF { IDLECF } ORECF { ORECF } NCF { NCF } FECF { FECF } PECF { PECF } } RDR { RDR; RDR { RDR } } TDR { TDR; TDR { TDR } } } } => { ... }; }
Extracts LPUART1 register tokens.