Macro drone_nrf_map::nrf_reg_tokens [−][src]
macro_rules! nrf_reg_tokens { reg::tokens! { /// Defines an index of nrf9160 register tokens. pub macro nrf_reg_tokens; use macro drone_cortexm::map::cortexm_reg_tokens; super::inner; crate::reg; /// Factory Information Configuration Registers pub mod FICR_S { TRNG90B_BYTES; TRNG90B_RCCUTOFF; TRNG90B_APCUTOFF; TRNG90B_STARTUP; TRNG90B_ROSC1; TRNG90B_ROSC2; TRNG90B_ROSC3; TRNG90B_ROSC4; TRIMCNF_0_ADDR; TRIMCNF_1_ADDR; TRIMCNF_2_ADDR; TRIMCNF_3_ADDR; TRIMCNF_4_ADDR; TRIMCNF_5_ADDR; TRIMCNF_6_ADDR; TRIMCNF_7_ADDR; TRIMCNF_8_ADDR; TRIMCNF_9_ADDR; TRIMCNF_10_ADDR; TRIMCNF_11_ADDR; TRIMCNF_12_ADDR; TRIMCNF_13_ADDR; TRIMCNF_14_ADDR; TRIMCNF_15_ADDR; TRIMCNF_16_ADDR; TRIMCNF_17_ADDR; TRIMCNF_18_ADDR; TRIMCNF_19_ADDR; TRIMCNF_20_ADDR; TRIMCNF_21_ADDR; TRIMCNF_22_ADDR; TRIMCNF_23_ADDR; TRIMCNF_24_ADDR; TRIMCNF_25_ADDR; TRIMCNF_26_ADDR; TRIMCNF_27_ADDR; TRIMCNF_28_ADDR; TRIMCNF_29_ADDR; TRIMCNF_30_ADDR; TRIMCNF_31_ADDR; TRIMCNF_32_ADDR; TRIMCNF_33_ADDR; TRIMCNF_34_ADDR; TRIMCNF_35_ADDR; TRIMCNF_36_ADDR; TRIMCNF_37_ADDR; TRIMCNF_38_ADDR; TRIMCNF_39_ADDR; TRIMCNF_40_ADDR; TRIMCNF_41_ADDR; TRIMCNF_42_ADDR; TRIMCNF_43_ADDR; TRIMCNF_44_ADDR; TRIMCNF_45_ADDR; TRIMCNF_46_ADDR; TRIMCNF_47_ADDR; TRIMCNF_48_ADDR; TRIMCNF_49_ADDR; TRIMCNF_50_ADDR; TRIMCNF_51_ADDR; TRIMCNF_52_ADDR; TRIMCNF_53_ADDR; TRIMCNF_54_ADDR; TRIMCNF_55_ADDR; TRIMCNF_56_ADDR; TRIMCNF_57_ADDR; TRIMCNF_58_ADDR; TRIMCNF_59_ADDR; TRIMCNF_60_ADDR; TRIMCNF_61_ADDR; TRIMCNF_62_ADDR; TRIMCNF_63_ADDR; TRIMCNF_64_ADDR; TRIMCNF_65_ADDR; TRIMCNF_66_ADDR; TRIMCNF_67_ADDR; TRIMCNF_68_ADDR; TRIMCNF_69_ADDR; TRIMCNF_70_ADDR; TRIMCNF_71_ADDR; TRIMCNF_72_ADDR; TRIMCNF_73_ADDR; TRIMCNF_74_ADDR; TRIMCNF_75_ADDR; TRIMCNF_76_ADDR; TRIMCNF_77_ADDR; TRIMCNF_78_ADDR; TRIMCNF_79_ADDR; TRIMCNF_80_ADDR; TRIMCNF_81_ADDR; TRIMCNF_82_ADDR; TRIMCNF_83_ADDR; TRIMCNF_84_ADDR; TRIMCNF_85_ADDR; TRIMCNF_86_ADDR; TRIMCNF_87_ADDR; TRIMCNF_88_ADDR; TRIMCNF_89_ADDR; TRIMCNF_90_ADDR; TRIMCNF_91_ADDR; TRIMCNF_92_ADDR; TRIMCNF_93_ADDR; TRIMCNF_94_ADDR; TRIMCNF_95_ADDR; TRIMCNF_96_ADDR; TRIMCNF_97_ADDR; TRIMCNF_98_ADDR; TRIMCNF_99_ADDR; TRIMCNF_100_ADDR; TRIMCNF_101_ADDR; TRIMCNF_102_ADDR; TRIMCNF_103_ADDR; TRIMCNF_104_ADDR; TRIMCNF_105_ADDR; TRIMCNF_106_ADDR; TRIMCNF_107_ADDR; TRIMCNF_108_ADDR; TRIMCNF_109_ADDR; TRIMCNF_110_ADDR; TRIMCNF_111_ADDR; TRIMCNF_112_ADDR; TRIMCNF_113_ADDR; TRIMCNF_114_ADDR; TRIMCNF_115_ADDR; TRIMCNF_116_ADDR; TRIMCNF_117_ADDR; TRIMCNF_118_ADDR; TRIMCNF_119_ADDR; TRIMCNF_120_ADDR; TRIMCNF_121_ADDR; TRIMCNF_122_ADDR; TRIMCNF_123_ADDR; TRIMCNF_124_ADDR; TRIMCNF_125_ADDR; TRIMCNF_126_ADDR; TRIMCNF_127_ADDR; TRIMCNF_128_ADDR; TRIMCNF_129_ADDR; TRIMCNF_130_ADDR; TRIMCNF_131_ADDR; TRIMCNF_132_ADDR; TRIMCNF_133_ADDR; TRIMCNF_134_ADDR; TRIMCNF_135_ADDR; TRIMCNF_136_ADDR; TRIMCNF_137_ADDR; TRIMCNF_138_ADDR; TRIMCNF_139_ADDR; TRIMCNF_140_ADDR; TRIMCNF_141_ADDR; TRIMCNF_142_ADDR; TRIMCNF_143_ADDR; TRIMCNF_144_ADDR; TRIMCNF_145_ADDR; TRIMCNF_146_ADDR; TRIMCNF_147_ADDR; TRIMCNF_148_ADDR; TRIMCNF_149_ADDR; TRIMCNF_150_ADDR; TRIMCNF_151_ADDR; TRIMCNF_152_ADDR; TRIMCNF_153_ADDR; TRIMCNF_154_ADDR; TRIMCNF_155_ADDR; TRIMCNF_156_ADDR; TRIMCNF_157_ADDR; TRIMCNF_158_ADDR; TRIMCNF_159_ADDR; TRIMCNF_160_ADDR; TRIMCNF_161_ADDR; TRIMCNF_162_ADDR; TRIMCNF_163_ADDR; TRIMCNF_164_ADDR; TRIMCNF_165_ADDR; TRIMCNF_166_ADDR; TRIMCNF_167_ADDR; TRIMCNF_168_ADDR; TRIMCNF_169_ADDR; TRIMCNF_170_ADDR; TRIMCNF_171_ADDR; TRIMCNF_172_ADDR; TRIMCNF_173_ADDR; TRIMCNF_174_ADDR; TRIMCNF_175_ADDR; TRIMCNF_176_ADDR; TRIMCNF_177_ADDR; TRIMCNF_178_ADDR; TRIMCNF_179_ADDR; TRIMCNF_180_ADDR; TRIMCNF_181_ADDR; TRIMCNF_182_ADDR; TRIMCNF_183_ADDR; TRIMCNF_184_ADDR; TRIMCNF_185_ADDR; TRIMCNF_186_ADDR; TRIMCNF_187_ADDR; TRIMCNF_188_ADDR; TRIMCNF_189_ADDR; TRIMCNF_190_ADDR; TRIMCNF_191_ADDR; TRIMCNF_192_ADDR; TRIMCNF_193_ADDR; TRIMCNF_194_ADDR; TRIMCNF_195_ADDR; TRIMCNF_196_ADDR; TRIMCNF_197_ADDR; TRIMCNF_198_ADDR; TRIMCNF_199_ADDR; TRIMCNF_200_ADDR; TRIMCNF_201_ADDR; TRIMCNF_202_ADDR; TRIMCNF_203_ADDR; TRIMCNF_204_ADDR; TRIMCNF_205_ADDR; TRIMCNF_206_ADDR; TRIMCNF_207_ADDR; TRIMCNF_208_ADDR; TRIMCNF_209_ADDR; TRIMCNF_210_ADDR; TRIMCNF_211_ADDR; TRIMCNF_212_ADDR; TRIMCNF_213_ADDR; TRIMCNF_214_ADDR; TRIMCNF_215_ADDR; TRIMCNF_216_ADDR; TRIMCNF_217_ADDR; TRIMCNF_218_ADDR; TRIMCNF_219_ADDR; TRIMCNF_220_ADDR; TRIMCNF_221_ADDR; TRIMCNF_222_ADDR; TRIMCNF_223_ADDR; TRIMCNF_224_ADDR; TRIMCNF_225_ADDR; TRIMCNF_226_ADDR; TRIMCNF_227_ADDR; TRIMCNF_228_ADDR; TRIMCNF_229_ADDR; TRIMCNF_230_ADDR; TRIMCNF_231_ADDR; TRIMCNF_232_ADDR; TRIMCNF_233_ADDR; TRIMCNF_234_ADDR; TRIMCNF_235_ADDR; TRIMCNF_236_ADDR; TRIMCNF_237_ADDR; TRIMCNF_238_ADDR; TRIMCNF_239_ADDR; TRIMCNF_240_ADDR; TRIMCNF_241_ADDR; TRIMCNF_242_ADDR; TRIMCNF_243_ADDR; TRIMCNF_244_ADDR; TRIMCNF_245_ADDR; TRIMCNF_246_ADDR; TRIMCNF_247_ADDR; TRIMCNF_248_ADDR; TRIMCNF_249_ADDR; TRIMCNF_250_ADDR; TRIMCNF_251_ADDR; TRIMCNF_252_ADDR; TRIMCNF_253_ADDR; TRIMCNF_254_ADDR; TRIMCNF_255_ADDR; TRIMCNF_0_DATA; TRIMCNF_1_DATA; TRIMCNF_2_DATA; TRIMCNF_3_DATA; TRIMCNF_4_DATA; TRIMCNF_5_DATA; TRIMCNF_6_DATA; TRIMCNF_7_DATA; TRIMCNF_8_DATA; TRIMCNF_9_DATA; TRIMCNF_10_DATA; TRIMCNF_11_DATA; TRIMCNF_12_DATA; TRIMCNF_13_DATA; TRIMCNF_14_DATA; TRIMCNF_15_DATA; TRIMCNF_16_DATA; TRIMCNF_17_DATA; TRIMCNF_18_DATA; TRIMCNF_19_DATA; TRIMCNF_20_DATA; TRIMCNF_21_DATA; TRIMCNF_22_DATA; TRIMCNF_23_DATA; TRIMCNF_24_DATA; TRIMCNF_25_DATA; TRIMCNF_26_DATA; TRIMCNF_27_DATA; TRIMCNF_28_DATA; TRIMCNF_29_DATA; TRIMCNF_30_DATA; TRIMCNF_31_DATA; TRIMCNF_32_DATA; TRIMCNF_33_DATA; TRIMCNF_34_DATA; TRIMCNF_35_DATA; TRIMCNF_36_DATA; TRIMCNF_37_DATA; TRIMCNF_38_DATA; TRIMCNF_39_DATA; TRIMCNF_40_DATA; TRIMCNF_41_DATA; TRIMCNF_42_DATA; TRIMCNF_43_DATA; TRIMCNF_44_DATA; TRIMCNF_45_DATA; TRIMCNF_46_DATA; TRIMCNF_47_DATA; TRIMCNF_48_DATA; TRIMCNF_49_DATA; TRIMCNF_50_DATA; TRIMCNF_51_DATA; TRIMCNF_52_DATA; TRIMCNF_53_DATA; TRIMCNF_54_DATA; TRIMCNF_55_DATA; TRIMCNF_56_DATA; TRIMCNF_57_DATA; TRIMCNF_58_DATA; TRIMCNF_59_DATA; TRIMCNF_60_DATA; TRIMCNF_61_DATA; TRIMCNF_62_DATA; TRIMCNF_63_DATA; TRIMCNF_64_DATA; TRIMCNF_65_DATA; TRIMCNF_66_DATA; TRIMCNF_67_DATA; TRIMCNF_68_DATA; TRIMCNF_69_DATA; TRIMCNF_70_DATA; TRIMCNF_71_DATA; TRIMCNF_72_DATA; TRIMCNF_73_DATA; TRIMCNF_74_DATA; TRIMCNF_75_DATA; TRIMCNF_76_DATA; TRIMCNF_77_DATA; TRIMCNF_78_DATA; TRIMCNF_79_DATA; TRIMCNF_80_DATA; TRIMCNF_81_DATA; TRIMCNF_82_DATA; TRIMCNF_83_DATA; TRIMCNF_84_DATA; TRIMCNF_85_DATA; TRIMCNF_86_DATA; TRIMCNF_87_DATA; TRIMCNF_88_DATA; TRIMCNF_89_DATA; TRIMCNF_90_DATA; TRIMCNF_91_DATA; TRIMCNF_92_DATA; TRIMCNF_93_DATA; TRIMCNF_94_DATA; TRIMCNF_95_DATA; TRIMCNF_96_DATA; TRIMCNF_97_DATA; TRIMCNF_98_DATA; TRIMCNF_99_DATA; TRIMCNF_100_DATA; TRIMCNF_101_DATA; TRIMCNF_102_DATA; TRIMCNF_103_DATA; TRIMCNF_104_DATA; TRIMCNF_105_DATA; TRIMCNF_106_DATA; TRIMCNF_107_DATA; TRIMCNF_108_DATA; TRIMCNF_109_DATA; TRIMCNF_110_DATA; TRIMCNF_111_DATA; TRIMCNF_112_DATA; TRIMCNF_113_DATA; TRIMCNF_114_DATA; TRIMCNF_115_DATA; TRIMCNF_116_DATA; TRIMCNF_117_DATA; TRIMCNF_118_DATA; TRIMCNF_119_DATA; TRIMCNF_120_DATA; TRIMCNF_121_DATA; TRIMCNF_122_DATA; TRIMCNF_123_DATA; TRIMCNF_124_DATA; TRIMCNF_125_DATA; TRIMCNF_126_DATA; TRIMCNF_127_DATA; TRIMCNF_128_DATA; TRIMCNF_129_DATA; TRIMCNF_130_DATA; TRIMCNF_131_DATA; TRIMCNF_132_DATA; TRIMCNF_133_DATA; TRIMCNF_134_DATA; TRIMCNF_135_DATA; TRIMCNF_136_DATA; TRIMCNF_137_DATA; TRIMCNF_138_DATA; TRIMCNF_139_DATA; TRIMCNF_140_DATA; TRIMCNF_141_DATA; TRIMCNF_142_DATA; TRIMCNF_143_DATA; TRIMCNF_144_DATA; TRIMCNF_145_DATA; TRIMCNF_146_DATA; TRIMCNF_147_DATA; TRIMCNF_148_DATA; TRIMCNF_149_DATA; TRIMCNF_150_DATA; TRIMCNF_151_DATA; TRIMCNF_152_DATA; TRIMCNF_153_DATA; TRIMCNF_154_DATA; TRIMCNF_155_DATA; TRIMCNF_156_DATA; TRIMCNF_157_DATA; TRIMCNF_158_DATA; TRIMCNF_159_DATA; TRIMCNF_160_DATA; TRIMCNF_161_DATA; TRIMCNF_162_DATA; TRIMCNF_163_DATA; TRIMCNF_164_DATA; TRIMCNF_165_DATA; TRIMCNF_166_DATA; TRIMCNF_167_DATA; TRIMCNF_168_DATA; TRIMCNF_169_DATA; TRIMCNF_170_DATA; TRIMCNF_171_DATA; TRIMCNF_172_DATA; TRIMCNF_173_DATA; TRIMCNF_174_DATA; TRIMCNF_175_DATA; TRIMCNF_176_DATA; TRIMCNF_177_DATA; TRIMCNF_178_DATA; TRIMCNF_179_DATA; TRIMCNF_180_DATA; TRIMCNF_181_DATA; TRIMCNF_182_DATA; TRIMCNF_183_DATA; TRIMCNF_184_DATA; TRIMCNF_185_DATA; TRIMCNF_186_DATA; TRIMCNF_187_DATA; TRIMCNF_188_DATA; TRIMCNF_189_DATA; TRIMCNF_190_DATA; TRIMCNF_191_DATA; TRIMCNF_192_DATA; TRIMCNF_193_DATA; TRIMCNF_194_DATA; TRIMCNF_195_DATA; TRIMCNF_196_DATA; TRIMCNF_197_DATA; TRIMCNF_198_DATA; TRIMCNF_199_DATA; TRIMCNF_200_DATA; TRIMCNF_201_DATA; TRIMCNF_202_DATA; TRIMCNF_203_DATA; TRIMCNF_204_DATA; TRIMCNF_205_DATA; TRIMCNF_206_DATA; TRIMCNF_207_DATA; TRIMCNF_208_DATA; TRIMCNF_209_DATA; TRIMCNF_210_DATA; TRIMCNF_211_DATA; TRIMCNF_212_DATA; TRIMCNF_213_DATA; TRIMCNF_214_DATA; TRIMCNF_215_DATA; TRIMCNF_216_DATA; TRIMCNF_217_DATA; TRIMCNF_218_DATA; TRIMCNF_219_DATA; TRIMCNF_220_DATA; TRIMCNF_221_DATA; TRIMCNF_222_DATA; TRIMCNF_223_DATA; TRIMCNF_224_DATA; TRIMCNF_225_DATA; TRIMCNF_226_DATA; TRIMCNF_227_DATA; TRIMCNF_228_DATA; TRIMCNF_229_DATA; TRIMCNF_230_DATA; TRIMCNF_231_DATA; TRIMCNF_232_DATA; TRIMCNF_233_DATA; TRIMCNF_234_DATA; TRIMCNF_235_DATA; TRIMCNF_236_DATA; TRIMCNF_237_DATA; TRIMCNF_238_DATA; TRIMCNF_239_DATA; TRIMCNF_240_DATA; TRIMCNF_241_DATA; TRIMCNF_242_DATA; TRIMCNF_243_DATA; TRIMCNF_244_DATA; TRIMCNF_245_DATA; TRIMCNF_246_DATA; TRIMCNF_247_DATA; TRIMCNF_248_DATA; TRIMCNF_249_DATA; TRIMCNF_250_DATA; TRIMCNF_251_DATA; TRIMCNF_252_DATA; TRIMCNF_253_DATA; TRIMCNF_254_DATA; TRIMCNF_255_DATA; INFO_DEVICEID_0; INFO_DEVICEID_1; INFO_PART; INFO_VARIANT; INFO_PACKAGE; INFO_RAM; INFO_FLASH; INFO_CODEPAGESIZE; INFO_CODESIZE; INFO_DEVICETYPE; } /// User information configuration registers User information configuration registers pub mod UICR_S { APPROTECT; XOSC32M; HFXOSRC; HFXOCNT; SECUREAPPROTECT; ERASEPROTECT; OTP_0; OTP_1; OTP_2; OTP_3; OTP_4; OTP_5; OTP_6; OTP_7; OTP_8; OTP_9; OTP_10; OTP_11; OTP_12; OTP_13; OTP_14; OTP_15; OTP_16; OTP_17; OTP_18; OTP_19; OTP_20; OTP_21; OTP_22; OTP_23; OTP_24; OTP_25; OTP_26; OTP_27; OTP_28; OTP_29; OTP_30; OTP_31; OTP_32; OTP_33; OTP_34; OTP_35; OTP_36; OTP_37; OTP_38; OTP_39; OTP_40; OTP_41; OTP_42; OTP_43; OTP_44; OTP_45; OTP_46; OTP_47; OTP_48; OTP_49; OTP_50; OTP_51; OTP_52; OTP_53; OTP_54; OTP_55; OTP_56; OTP_57; OTP_58; OTP_59; OTP_60; OTP_61; OTP_62; OTP_63; OTP_64; OTP_65; OTP_66; OTP_67; OTP_68; OTP_69; OTP_70; OTP_71; OTP_72; OTP_73; OTP_74; OTP_75; OTP_76; OTP_77; OTP_78; OTP_79; OTP_80; OTP_81; OTP_82; OTP_83; OTP_84; OTP_85; OTP_86; OTP_87; OTP_88; OTP_89; OTP_90; OTP_91; OTP_92; OTP_93; OTP_94; OTP_95; OTP_96; OTP_97; OTP_98; OTP_99; OTP_100; OTP_101; OTP_102; OTP_103; OTP_104; OTP_105; OTP_106; OTP_107; OTP_108; OTP_109; OTP_110; OTP_111; OTP_112; OTP_113; OTP_114; OTP_115; OTP_116; OTP_117; OTP_118; OTP_119; OTP_120; OTP_121; OTP_122; OTP_123; OTP_124; OTP_125; OTP_126; OTP_127; OTP_128; OTP_129; OTP_130; OTP_131; OTP_132; OTP_133; OTP_134; OTP_135; OTP_136; OTP_137; OTP_138; OTP_139; OTP_140; OTP_141; OTP_142; OTP_143; OTP_144; OTP_145; OTP_146; OTP_147; OTP_148; OTP_149; OTP_150; OTP_151; OTP_152; OTP_153; OTP_154; OTP_155; OTP_156; OTP_157; OTP_158; OTP_159; OTP_160; OTP_161; OTP_162; OTP_163; OTP_164; OTP_165; OTP_166; OTP_167; OTP_168; OTP_169; OTP_170; OTP_171; OTP_172; OTP_173; OTP_174; OTP_175; OTP_176; OTP_177; OTP_178; OTP_179; OTP_180; OTP_181; OTP_182; OTP_183; OTP_184; OTP_185; OTP_186; OTP_187; OTP_188; OTP_189; } /// Trace and debug control pub mod TAD_S { CLOCKSTART; CLOCKSTOP; ENABLE; TRACEPORTSPEED; PSEL_TRACECLK; PSEL_TRACEDATA0; PSEL_TRACEDATA1; PSEL_TRACEDATA2; PSEL_TRACEDATA3; } /// System protection unit pub mod SPU_S { EVENTS_RAMACCERR; EVENTS_FLASHACCERR; EVENTS_PERIPHACCERR; PUBLISH_RAMACCERR; PUBLISH_FLASHACCERR; PUBLISH_PERIPHACCERR; INTEN; INTENSET; INTENCLR; CAP; PERIPHID_0_PERM; PERIPHID_1_PERM; PERIPHID_2_PERM; PERIPHID_3_PERM; PERIPHID_4_PERM; PERIPHID_5_PERM; PERIPHID_6_PERM; PERIPHID_7_PERM; PERIPHID_8_PERM; PERIPHID_9_PERM; PERIPHID_10_PERM; PERIPHID_11_PERM; PERIPHID_12_PERM; PERIPHID_13_PERM; PERIPHID_14_PERM; PERIPHID_15_PERM; PERIPHID_16_PERM; PERIPHID_17_PERM; PERIPHID_18_PERM; PERIPHID_19_PERM; PERIPHID_20_PERM; PERIPHID_21_PERM; PERIPHID_22_PERM; PERIPHID_23_PERM; PERIPHID_24_PERM; PERIPHID_25_PERM; PERIPHID_26_PERM; PERIPHID_27_PERM; PERIPHID_28_PERM; PERIPHID_29_PERM; PERIPHID_30_PERM; PERIPHID_31_PERM; PERIPHID_32_PERM; PERIPHID_33_PERM; PERIPHID_34_PERM; PERIPHID_35_PERM; PERIPHID_36_PERM; PERIPHID_37_PERM; PERIPHID_38_PERM; PERIPHID_39_PERM; PERIPHID_40_PERM; PERIPHID_41_PERM; PERIPHID_42_PERM; PERIPHID_43_PERM; PERIPHID_44_PERM; PERIPHID_45_PERM; PERIPHID_46_PERM; PERIPHID_47_PERM; PERIPHID_48_PERM; PERIPHID_49_PERM; PERIPHID_50_PERM; PERIPHID_51_PERM; PERIPHID_52_PERM; PERIPHID_53_PERM; PERIPHID_54_PERM; PERIPHID_55_PERM; PERIPHID_56_PERM; PERIPHID_57_PERM; PERIPHID_58_PERM; PERIPHID_59_PERM; PERIPHID_60_PERM; PERIPHID_61_PERM; PERIPHID_62_PERM; PERIPHID_63_PERM; PERIPHID_64_PERM; PERIPHID_65_PERM; PERIPHID_66_PERM; RAMREGION_0_PERM; RAMREGION_1_PERM; RAMREGION_2_PERM; RAMREGION_3_PERM; RAMREGION_4_PERM; RAMREGION_5_PERM; RAMREGION_6_PERM; RAMREGION_7_PERM; RAMREGION_8_PERM; RAMREGION_9_PERM; RAMREGION_10_PERM; RAMREGION_11_PERM; RAMREGION_12_PERM; RAMREGION_13_PERM; RAMREGION_14_PERM; RAMREGION_15_PERM; RAMREGION_16_PERM; RAMREGION_17_PERM; RAMREGION_18_PERM; RAMREGION_19_PERM; RAMREGION_20_PERM; RAMREGION_21_PERM; RAMREGION_22_PERM; RAMREGION_23_PERM; RAMREGION_24_PERM; RAMREGION_25_PERM; RAMREGION_26_PERM; RAMREGION_27_PERM; RAMREGION_28_PERM; RAMREGION_29_PERM; RAMREGION_30_PERM; RAMREGION_31_PERM; FLASHREGION_0_PERM; FLASHREGION_1_PERM; FLASHREGION_2_PERM; FLASHREGION_3_PERM; FLASHREGION_4_PERM; FLASHREGION_5_PERM; FLASHREGION_6_PERM; FLASHREGION_7_PERM; FLASHREGION_8_PERM; FLASHREGION_9_PERM; FLASHREGION_10_PERM; FLASHREGION_11_PERM; FLASHREGION_12_PERM; FLASHREGION_13_PERM; FLASHREGION_14_PERM; FLASHREGION_15_PERM; FLASHREGION_16_PERM; FLASHREGION_17_PERM; FLASHREGION_18_PERM; FLASHREGION_19_PERM; FLASHREGION_20_PERM; FLASHREGION_21_PERM; FLASHREGION_22_PERM; FLASHREGION_23_PERM; FLASHREGION_24_PERM; FLASHREGION_25_PERM; FLASHREGION_26_PERM; FLASHREGION_27_PERM; FLASHREGION_28_PERM; FLASHREGION_29_PERM; FLASHREGION_30_PERM; FLASHREGION_31_PERM; RAMNSC_0_REGION; RAMNSC_1_REGION; RAMNSC_0_SIZE; RAMNSC_1_SIZE; FLASHNSC_0_REGION; FLASHNSC_1_REGION; FLASHNSC_0_SIZE; FLASHNSC_1_SIZE; GPIOPORT_0_PERM; GPIOPORT_0_LOCK; DPPI_0_PERM; DPPI_0_LOCK; EXTDOMAIN_0_PERM; } /// Voltage regulators control 0 pub mod REGULATORS_NS { SYSTEMOFF; DCDCEN; } /// Voltage regulators control 1 pub mod REGULATORS_S { !SYSTEMOFF; !DCDCEN; } /// Clock management 0 pub mod CLOCK_NS { TASKS_HFCLKSTART; TASKS_HFCLKSTOP; TASKS_LFCLKSTART; TASKS_LFCLKSTOP; SUBSCRIBE_HFCLKSTART; SUBSCRIBE_HFCLKSTOP; SUBSCRIBE_LFCLKSTART; SUBSCRIBE_LFCLKSTOP; EVENTS_HFCLKSTARTED; EVENTS_LFCLKSTARTED; PUBLISH_HFCLKSTARTED; PUBLISH_LFCLKSTARTED; INTEN; INTENSET; INTENCLR; INTPEND; HFCLKRUN; HFCLKSTAT; LFCLKRUN; LFCLKSTAT; LFCLKSRCCOPY; LFCLKSRC; } /// Clock management 1 pub mod CLOCK_S { !TASKS_HFCLKSTART; !TASKS_HFCLKSTOP; !TASKS_LFCLKSTART; !TASKS_LFCLKSTOP; !SUBSCRIBE_HFCLKSTART; !SUBSCRIBE_HFCLKSTOP; !SUBSCRIBE_LFCLKSTART; !SUBSCRIBE_LFCLKSTOP; !EVENTS_HFCLKSTARTED; !EVENTS_LFCLKSTARTED; !PUBLISH_HFCLKSTARTED; !PUBLISH_LFCLKSTARTED; !INTEN; !INTENSET; !INTENCLR; !INTPEND; !HFCLKRUN; !HFCLKSTAT; !LFCLKRUN; !LFCLKSTAT; !LFCLKSRCCOPY; !LFCLKSRC; } /// Power control 0 pub mod POWER_NS { !INTEN; !INTENSET; !INTENCLR; TASKS_CONSTLAT; TASKS_LOWPWR; SUBSCRIBE_CONSTLAT; SUBSCRIBE_LOWPWR; EVENTS_POFWARN; EVENTS_SLEEPENTER; EVENTS_SLEEPEXIT; PUBLISH_POFWARN; PUBLISH_SLEEPENTER; PUBLISH_SLEEPEXIT; RESETREAS; POWERSTATUS; GPREGRET_0; GPREGRET_1; } /// Power control 1 pub mod POWER_S { !INTEN; !INTENSET; !INTENCLR; !TASKS_CONSTLAT; !TASKS_LOWPWR; !SUBSCRIBE_CONSTLAT; !SUBSCRIBE_LOWPWR; !EVENTS_POFWARN; !EVENTS_SLEEPENTER; !EVENTS_SLEEPEXIT; !PUBLISH_POFWARN; !PUBLISH_SLEEPENTER; !PUBLISH_SLEEPEXIT; !RESETREAS; !POWERSTATUS; !GPREGRET_0; !GPREGRET_1; } /// Control access port pub mod CTRL_AP_PERI_S { ERASEPROTECT_LOCK; ERASEPROTECT_DISABLE; MAILBOX_RXDATA; MAILBOX_RXSTATUS; MAILBOX_TXDATA; MAILBOX_TXSTATUS; } /// Serial Peripheral Interface Master with EasyDMA 0 pub mod SPIM0_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 1 pub mod SPIM0_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 0 pub mod TWIM0_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 pub mod TWIS0_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 1 pub mod TWIM0_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 pub mod TWIS0_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 0 pub mod SPIS0_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 0 pub mod UARTE0_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 1 pub mod SPIS0_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 1 pub mod UARTE0_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// Serial Peripheral Interface Master with EasyDMA 2 pub mod SPIM1_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 3 pub mod SPIM1_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 2 pub mod TWIM1_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 2 pub mod TWIS1_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 3 pub mod TWIM1_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 3 pub mod TWIS1_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 2 pub mod SPIS1_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 2 pub mod UARTE1_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 3 pub mod SPIS1_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 3 pub mod UARTE1_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// Serial Peripheral Interface Master with EasyDMA 4 pub mod SPIM2_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 5 pub mod SPIM2_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 4 pub mod TWIM2_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 4 pub mod TWIS2_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 5 pub mod TWIM2_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 5 pub mod TWIS2_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 4 pub mod SPIS2_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 4 pub mod UARTE2_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 5 pub mod SPIS2_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 5 pub mod UARTE2_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// Serial Peripheral Interface Master with EasyDMA 6 pub mod SPIM3_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 7 pub mod SPIM3_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 6 pub mod TWIM3_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 6 pub mod TWIS3_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 7 pub mod TWIM3_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 7 pub mod TWIS3_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 6 pub mod SPIS3_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 6 pub mod UARTE3_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 7 pub mod SPIS3_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 7 pub mod UARTE3_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// GPIO Tasks and Events 0 pub mod GPIOTE0_S { TASKS_OUT_0; TASKS_OUT_1; TASKS_OUT_2; TASKS_OUT_3; TASKS_OUT_4; TASKS_OUT_5; TASKS_OUT_6; TASKS_OUT_7; TASKS_SET_0; TASKS_SET_1; TASKS_SET_2; TASKS_SET_3; TASKS_SET_4; TASKS_SET_5; TASKS_SET_6; TASKS_SET_7; TASKS_CLR_0; TASKS_CLR_1; TASKS_CLR_2; TASKS_CLR_3; TASKS_CLR_4; TASKS_CLR_5; TASKS_CLR_6; TASKS_CLR_7; SUBSCRIBE_OUT_0; SUBSCRIBE_OUT_1; SUBSCRIBE_OUT_2; SUBSCRIBE_OUT_3; SUBSCRIBE_OUT_4; SUBSCRIBE_OUT_5; SUBSCRIBE_OUT_6; SUBSCRIBE_OUT_7; SUBSCRIBE_SET_0; SUBSCRIBE_SET_1; SUBSCRIBE_SET_2; SUBSCRIBE_SET_3; SUBSCRIBE_SET_4; SUBSCRIBE_SET_5; SUBSCRIBE_SET_6; SUBSCRIBE_SET_7; SUBSCRIBE_CLR_0; SUBSCRIBE_CLR_1; SUBSCRIBE_CLR_2; SUBSCRIBE_CLR_3; SUBSCRIBE_CLR_4; SUBSCRIBE_CLR_5; SUBSCRIBE_CLR_6; SUBSCRIBE_CLR_7; EVENTS_IN_0; EVENTS_IN_1; EVENTS_IN_2; EVENTS_IN_3; EVENTS_IN_4; EVENTS_IN_5; EVENTS_IN_6; EVENTS_IN_7; EVENTS_PORT; PUBLISH_IN_0; PUBLISH_IN_1; PUBLISH_IN_2; PUBLISH_IN_3; PUBLISH_IN_4; PUBLISH_IN_5; PUBLISH_IN_6; PUBLISH_IN_7; PUBLISH_PORT; INTENSET; INTENCLR; CONFIG_0; CONFIG_1; CONFIG_2; CONFIG_3; CONFIG_4; CONFIG_5; CONFIG_6; CONFIG_7; } /// Analog to Digital Converter 0 pub mod SAADC_NS { TASKS_START; TASKS_SAMPLE; TASKS_STOP; TASKS_CALIBRATEOFFSET; SUBSCRIBE_START; SUBSCRIBE_SAMPLE; SUBSCRIBE_STOP; SUBSCRIBE_CALIBRATEOFFSET; EVENTS_STARTED; EVENTS_END; EVENTS_DONE; EVENTS_RESULTDONE; EVENTS_CALIBRATEDONE; EVENTS_STOPPED; PUBLISH_STARTED; PUBLISH_END; PUBLISH_DONE; PUBLISH_RESULTDONE; PUBLISH_CALIBRATEDONE; PUBLISH_STOPPED; INTEN; INTENSET; INTENCLR; STATUS; ENABLE; RESOLUTION; OVERSAMPLE; SAMPLERATE; RESULT_PTR; RESULT_MAXCNT; RESULT_AMOUNT; CH_0_PSELP; CH_1_PSELP; CH_2_PSELP; CH_3_PSELP; CH_4_PSELP; CH_5_PSELP; CH_6_PSELP; CH_7_PSELP; CH_0_PSELN; CH_1_PSELN; CH_2_PSELN; CH_3_PSELN; CH_4_PSELN; CH_5_PSELN; CH_6_PSELN; CH_7_PSELN; CH_0_CONFIG; CH_1_CONFIG; CH_2_CONFIG; CH_3_CONFIG; CH_4_CONFIG; CH_5_CONFIG; CH_6_CONFIG; CH_7_CONFIG; CH_0_LIMIT; CH_1_LIMIT; CH_2_LIMIT; CH_3_LIMIT; CH_4_LIMIT; CH_5_LIMIT; CH_6_LIMIT; CH_7_LIMIT; PUBLISH_CH_0_LIMITH; PUBLISH_CH_1_LIMITH; PUBLISH_CH_2_LIMITH; PUBLISH_CH_3_LIMITH; PUBLISH_CH_4_LIMITH; PUBLISH_CH_5_LIMITH; PUBLISH_CH_6_LIMITH; PUBLISH_CH_7_LIMITH; PUBLISH_CH_0_LIMITL; PUBLISH_CH_1_LIMITL; PUBLISH_CH_2_LIMITL; PUBLISH_CH_3_LIMITL; PUBLISH_CH_4_LIMITL; PUBLISH_CH_5_LIMITL; PUBLISH_CH_6_LIMITL; PUBLISH_CH_7_LIMITL; EVENTS_CH_0_LIMITH; EVENTS_CH_1_LIMITH; EVENTS_CH_2_LIMITH; EVENTS_CH_3_LIMITH; EVENTS_CH_4_LIMITH; EVENTS_CH_5_LIMITH; EVENTS_CH_6_LIMITH; EVENTS_CH_7_LIMITH; EVENTS_CH_0_LIMITL; EVENTS_CH_1_LIMITL; EVENTS_CH_2_LIMITL; EVENTS_CH_3_LIMITL; EVENTS_CH_4_LIMITL; EVENTS_CH_5_LIMITL; EVENTS_CH_6_LIMITL; EVENTS_CH_7_LIMITL; } /// Analog to Digital Converter 1 pub mod SAADC_S { !TASKS_START; !TASKS_SAMPLE; !TASKS_STOP; !TASKS_CALIBRATEOFFSET; !SUBSCRIBE_START; !SUBSCRIBE_SAMPLE; !SUBSCRIBE_STOP; !SUBSCRIBE_CALIBRATEOFFSET; !EVENTS_STARTED; !EVENTS_END; !EVENTS_DONE; !EVENTS_RESULTDONE; !EVENTS_CALIBRATEDONE; !EVENTS_STOPPED; !PUBLISH_STARTED; !PUBLISH_END; !PUBLISH_DONE; !PUBLISH_RESULTDONE; !PUBLISH_CALIBRATEDONE; !PUBLISH_STOPPED; !INTEN; !INTENSET; !INTENCLR; !STATUS; !ENABLE; !RESOLUTION; !OVERSAMPLE; !SAMPLERATE; !RESULT_PTR; !RESULT_MAXCNT; !RESULT_AMOUNT; !CH_0_PSELP; !CH_1_PSELP; !CH_2_PSELP; !CH_3_PSELP; !CH_4_PSELP; !CH_5_PSELP; !CH_6_PSELP; !CH_7_PSELP; !CH_0_PSELN; !CH_1_PSELN; !CH_2_PSELN; !CH_3_PSELN; !CH_4_PSELN; !CH_5_PSELN; !CH_6_PSELN; !CH_7_PSELN; !CH_0_CONFIG; !CH_1_CONFIG; !CH_2_CONFIG; !CH_3_CONFIG; !CH_4_CONFIG; !CH_5_CONFIG; !CH_6_CONFIG; !CH_7_CONFIG; !CH_0_LIMIT; !CH_1_LIMIT; !CH_2_LIMIT; !CH_3_LIMIT; !CH_4_LIMIT; !CH_5_LIMIT; !CH_6_LIMIT; !CH_7_LIMIT; !PUBLISH_CH_0_LIMITH; !PUBLISH_CH_1_LIMITH; !PUBLISH_CH_2_LIMITH; !PUBLISH_CH_3_LIMITH; !PUBLISH_CH_4_LIMITH; !PUBLISH_CH_5_LIMITH; !PUBLISH_CH_6_LIMITH; !PUBLISH_CH_7_LIMITH; !PUBLISH_CH_0_LIMITL; !PUBLISH_CH_1_LIMITL; !PUBLISH_CH_2_LIMITL; !PUBLISH_CH_3_LIMITL; !PUBLISH_CH_4_LIMITL; !PUBLISH_CH_5_LIMITL; !PUBLISH_CH_6_LIMITL; !PUBLISH_CH_7_LIMITL; !EVENTS_CH_0_LIMITH; !EVENTS_CH_1_LIMITH; !EVENTS_CH_2_LIMITH; !EVENTS_CH_3_LIMITH; !EVENTS_CH_4_LIMITH; !EVENTS_CH_5_LIMITH; !EVENTS_CH_6_LIMITH; !EVENTS_CH_7_LIMITH; !EVENTS_CH_0_LIMITL; !EVENTS_CH_1_LIMITL; !EVENTS_CH_2_LIMITL; !EVENTS_CH_3_LIMITL; !EVENTS_CH_4_LIMITL; !EVENTS_CH_5_LIMITL; !EVENTS_CH_6_LIMITL; !EVENTS_CH_7_LIMITL; } /// Timer/Counter 0 pub mod TIMER0_NS { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_COUNT; SUBSCRIBE_CLEAR; SUBSCRIBE_SHUTDOWN; SUBSCRIBE_CAPTURE_0; SUBSCRIBE_CAPTURE_1; SUBSCRIBE_CAPTURE_2; SUBSCRIBE_CAPTURE_3; SUBSCRIBE_CAPTURE_4; SUBSCRIBE_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; PUBLISH_COMPARE_4; PUBLISH_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; ONESHOTEN_0; ONESHOTEN_1; ONESHOTEN_2; ONESHOTEN_3; ONESHOTEN_4; ONESHOTEN_5; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 1 pub mod TIMER0_S { !TASKS_START; !TASKS_STOP; !TASKS_COUNT; !TASKS_CLEAR; !TASKS_SHUTDOWN; !TASKS_CAPTURE_0; !TASKS_CAPTURE_1; !TASKS_CAPTURE_2; !TASKS_CAPTURE_3; !TASKS_CAPTURE_4; !TASKS_CAPTURE_5; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_COUNT; !SUBSCRIBE_CLEAR; !SUBSCRIBE_SHUTDOWN; !SUBSCRIBE_CAPTURE_0; !SUBSCRIBE_CAPTURE_1; !SUBSCRIBE_CAPTURE_2; !SUBSCRIBE_CAPTURE_3; !SUBSCRIBE_CAPTURE_4; !SUBSCRIBE_CAPTURE_5; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !EVENTS_COMPARE_4; !EVENTS_COMPARE_5; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !PUBLISH_COMPARE_4; !PUBLISH_COMPARE_5; !SHORTS; !INTENSET; !INTENCLR; !MODE; !BITMODE; !PRESCALER; !ONESHOTEN_0; !ONESHOTEN_1; !ONESHOTEN_2; !ONESHOTEN_3; !ONESHOTEN_4; !ONESHOTEN_5; !CC_0; !CC_1; !CC_2; !CC_3; !CC_4; !CC_5; } /// Timer/Counter 2 pub mod TIMER1_NS { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_COUNT; SUBSCRIBE_CLEAR; SUBSCRIBE_SHUTDOWN; SUBSCRIBE_CAPTURE_0; SUBSCRIBE_CAPTURE_1; SUBSCRIBE_CAPTURE_2; SUBSCRIBE_CAPTURE_3; SUBSCRIBE_CAPTURE_4; SUBSCRIBE_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; PUBLISH_COMPARE_4; PUBLISH_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; ONESHOTEN_0; ONESHOTEN_1; ONESHOTEN_2; ONESHOTEN_3; ONESHOTEN_4; ONESHOTEN_5; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 3 pub mod TIMER1_S { !TASKS_START; !TASKS_STOP; !TASKS_COUNT; !TASKS_CLEAR; !TASKS_SHUTDOWN; !TASKS_CAPTURE_0; !TASKS_CAPTURE_1; !TASKS_CAPTURE_2; !TASKS_CAPTURE_3; !TASKS_CAPTURE_4; !TASKS_CAPTURE_5; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_COUNT; !SUBSCRIBE_CLEAR; !SUBSCRIBE_SHUTDOWN; !SUBSCRIBE_CAPTURE_0; !SUBSCRIBE_CAPTURE_1; !SUBSCRIBE_CAPTURE_2; !SUBSCRIBE_CAPTURE_3; !SUBSCRIBE_CAPTURE_4; !SUBSCRIBE_CAPTURE_5; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !EVENTS_COMPARE_4; !EVENTS_COMPARE_5; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !PUBLISH_COMPARE_4; !PUBLISH_COMPARE_5; !SHORTS; !INTENSET; !INTENCLR; !MODE; !BITMODE; !PRESCALER; !ONESHOTEN_0; !ONESHOTEN_1; !ONESHOTEN_2; !ONESHOTEN_3; !ONESHOTEN_4; !ONESHOTEN_5; !CC_0; !CC_1; !CC_2; !CC_3; !CC_4; !CC_5; } /// Timer/Counter 4 pub mod TIMER2_NS { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_COUNT; SUBSCRIBE_CLEAR; SUBSCRIBE_SHUTDOWN; SUBSCRIBE_CAPTURE_0; SUBSCRIBE_CAPTURE_1; SUBSCRIBE_CAPTURE_2; SUBSCRIBE_CAPTURE_3; SUBSCRIBE_CAPTURE_4; SUBSCRIBE_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; PUBLISH_COMPARE_4; PUBLISH_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; ONESHOTEN_0; ONESHOTEN_1; ONESHOTEN_2; ONESHOTEN_3; ONESHOTEN_4; ONESHOTEN_5; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 5 pub mod TIMER2_S { !TASKS_START; !TASKS_STOP; !TASKS_COUNT; !TASKS_CLEAR; !TASKS_SHUTDOWN; !TASKS_CAPTURE_0; !TASKS_CAPTURE_1; !TASKS_CAPTURE_2; !TASKS_CAPTURE_3; !TASKS_CAPTURE_4; !TASKS_CAPTURE_5; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_COUNT; !SUBSCRIBE_CLEAR; !SUBSCRIBE_SHUTDOWN; !SUBSCRIBE_CAPTURE_0; !SUBSCRIBE_CAPTURE_1; !SUBSCRIBE_CAPTURE_2; !SUBSCRIBE_CAPTURE_3; !SUBSCRIBE_CAPTURE_4; !SUBSCRIBE_CAPTURE_5; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !EVENTS_COMPARE_4; !EVENTS_COMPARE_5; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !PUBLISH_COMPARE_4; !PUBLISH_COMPARE_5; !SHORTS; !INTENSET; !INTENCLR; !MODE; !BITMODE; !PRESCALER; !ONESHOTEN_0; !ONESHOTEN_1; !ONESHOTEN_2; !ONESHOTEN_3; !ONESHOTEN_4; !ONESHOTEN_5; !CC_0; !CC_1; !CC_2; !CC_3; !CC_4; !CC_5; } /// Real-time counter 0 pub mod RTC0_NS { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_CLEAR; SUBSCRIBE_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; PUBLISH_TICK; PUBLISH_OVRFLW; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Real-time counter 1 pub mod RTC0_S { !TASKS_START; !TASKS_STOP; !TASKS_CLEAR; !TASKS_TRIGOVRFLW; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_CLEAR; !SUBSCRIBE_TRIGOVRFLW; !EVENTS_TICK; !EVENTS_OVRFLW; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !PUBLISH_TICK; !PUBLISH_OVRFLW; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !INTENSET; !INTENCLR; !EVTEN; !EVTENSET; !EVTENCLR; !COUNTER; !PRESCALER; !CC_0; !CC_1; !CC_2; !CC_3; } /// Real-time counter 2 pub mod RTC1_NS { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_CLEAR; SUBSCRIBE_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; PUBLISH_TICK; PUBLISH_OVRFLW; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Real-time counter 3 pub mod RTC1_S { !TASKS_START; !TASKS_STOP; !TASKS_CLEAR; !TASKS_TRIGOVRFLW; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_CLEAR; !SUBSCRIBE_TRIGOVRFLW; !EVENTS_TICK; !EVENTS_OVRFLW; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !PUBLISH_TICK; !PUBLISH_OVRFLW; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !INTENSET; !INTENCLR; !EVTEN; !EVTENSET; !EVTENCLR; !COUNTER; !PRESCALER; !CC_0; !CC_1; !CC_2; !CC_3; } /// Distributed Programmable Peripheral Interconnect Controller 0 pub mod DPPIC_NS { CHEN; CHENSET; CHENCLR; CHG_0; CHG_1; CHG_2; CHG_3; CHG_4; CHG_5; SUBSCRIBE_CHG_0_EN; SUBSCRIBE_CHG_1_EN; SUBSCRIBE_CHG_2_EN; SUBSCRIBE_CHG_3_EN; SUBSCRIBE_CHG_4_EN; SUBSCRIBE_CHG_5_EN; SUBSCRIBE_CHG_0_DIS; SUBSCRIBE_CHG_1_DIS; SUBSCRIBE_CHG_2_DIS; SUBSCRIBE_CHG_3_DIS; SUBSCRIBE_CHG_4_DIS; SUBSCRIBE_CHG_5_DIS; TASKS_CHG_0_EN; TASKS_CHG_1_EN; TASKS_CHG_2_EN; TASKS_CHG_3_EN; TASKS_CHG_4_EN; TASKS_CHG_5_EN; TASKS_CHG_0_DIS; TASKS_CHG_1_DIS; TASKS_CHG_2_DIS; TASKS_CHG_3_DIS; TASKS_CHG_4_DIS; TASKS_CHG_5_DIS; } /// Distributed Programmable Peripheral Interconnect Controller 1 pub mod DPPIC_S { !CHEN; !CHENSET; !CHENCLR; !CHG_0; !CHG_1; !CHG_2; !CHG_3; !CHG_4; !CHG_5; !SUBSCRIBE_CHG_0_EN; !SUBSCRIBE_CHG_1_EN; !SUBSCRIBE_CHG_2_EN; !SUBSCRIBE_CHG_3_EN; !SUBSCRIBE_CHG_4_EN; !SUBSCRIBE_CHG_5_EN; !SUBSCRIBE_CHG_0_DIS; !SUBSCRIBE_CHG_1_DIS; !SUBSCRIBE_CHG_2_DIS; !SUBSCRIBE_CHG_3_DIS; !SUBSCRIBE_CHG_4_DIS; !SUBSCRIBE_CHG_5_DIS; !TASKS_CHG_0_EN; !TASKS_CHG_1_EN; !TASKS_CHG_2_EN; !TASKS_CHG_3_EN; !TASKS_CHG_4_EN; !TASKS_CHG_5_EN; !TASKS_CHG_0_DIS; !TASKS_CHG_1_DIS; !TASKS_CHG_2_DIS; !TASKS_CHG_3_DIS; !TASKS_CHG_4_DIS; !TASKS_CHG_5_DIS; } /// Watchdog Timer 0 pub mod WDT_NS { TASKS_START; SUBSCRIBE_START; EVENTS_TIMEOUT; PUBLISH_TIMEOUT; INTENSET; INTENCLR; RUNSTATUS; REQSTATUS; CRV; RREN; CONFIG; RR_0; RR_1; RR_2; RR_3; RR_4; RR_5; RR_6; RR_7; } /// Watchdog Timer 1 pub mod WDT_S { !TASKS_START; !SUBSCRIBE_START; !EVENTS_TIMEOUT; !PUBLISH_TIMEOUT; !INTENSET; !INTENCLR; !RUNSTATUS; !REQSTATUS; !CRV; !RREN; !CONFIG; !RR_0; !RR_1; !RR_2; !RR_3; !RR_4; !RR_5; !RR_6; !RR_7; } /// Event generator unit 0 pub mod EGU0_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 1 pub mod EGU0_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 2 pub mod EGU1_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 3 pub mod EGU1_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 4 pub mod EGU2_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 5 pub mod EGU2_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 6 pub mod EGU3_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 7 pub mod EGU3_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 8 pub mod EGU4_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 9 pub mod EGU4_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 10 pub mod EGU5_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 11 pub mod EGU5_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Pulse width modulation unit 0 pub mod PWM0_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 1 pub mod PWM0_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse width modulation unit 2 pub mod PWM1_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 3 pub mod PWM1_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse width modulation unit 4 pub mod PWM2_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 5 pub mod PWM2_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse width modulation unit 6 pub mod PWM3_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 7 pub mod PWM3_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse Density Modulation (Digital Microphone) Interface 0 pub mod PDM_NS { TASKS_START; TASKS_STOP; SUBSCRIBE_START; SUBSCRIBE_STOP; EVENTS_STARTED; EVENTS_STOPPED; EVENTS_END; PUBLISH_STARTED; PUBLISH_STOPPED; PUBLISH_END; INTEN; INTENSET; INTENCLR; ENABLE; PDMCLKCTRL; MODE; GAINL; GAINR; RATIO; SAMPLE_PTR; SAMPLE_MAXCNT; PSEL_CLK; PSEL_DIN; } /// Pulse Density Modulation (Digital Microphone) Interface 1 pub mod PDM_S { !TASKS_START; !TASKS_STOP; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !EVENTS_STARTED; !EVENTS_STOPPED; !EVENTS_END; !PUBLISH_STARTED; !PUBLISH_STOPPED; !PUBLISH_END; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !PDMCLKCTRL; !MODE; !GAINL; !GAINR; !RATIO; !SAMPLE_PTR; !SAMPLE_MAXCNT; !PSEL_CLK; !PSEL_DIN; } /// Inter-IC Sound 0 pub mod I2S_NS { TASKS_START; TASKS_STOP; SUBSCRIBE_START; SUBSCRIBE_STOP; EVENTS_RXPTRUPD; EVENTS_STOPPED; EVENTS_TXPTRUPD; PUBLISH_RXPTRUPD; PUBLISH_STOPPED; PUBLISH_TXPTRUPD; INTEN; INTENSET; INTENCLR; ENABLE; PSEL_MCK; PSEL_SCK; PSEL_LRCK; PSEL_SDIN; PSEL_SDOUT; RXTXD_MAXCNT; TXD_PTR; RXD_PTR; CONFIG_MODE; CONFIG_RXEN; CONFIG_TXEN; CONFIG_MCKEN; CONFIG_MCKFREQ; CONFIG_RATIO; CONFIG_SWIDTH; CONFIG_ALIGN; CONFIG_FORMAT; CONFIG_CHANNELS; } /// Inter-IC Sound 1 pub mod I2S_S { !TASKS_START; !TASKS_STOP; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !EVENTS_RXPTRUPD; !EVENTS_STOPPED; !EVENTS_TXPTRUPD; !PUBLISH_RXPTRUPD; !PUBLISH_STOPPED; !PUBLISH_TXPTRUPD; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !PSEL_MCK; !PSEL_SCK; !PSEL_LRCK; !PSEL_SDIN; !PSEL_SDOUT; !RXTXD_MAXCNT; !TXD_PTR; !RXD_PTR; !CONFIG_MODE; !CONFIG_RXEN; !CONFIG_TXEN; !CONFIG_MCKEN; !CONFIG_MCKFREQ; !CONFIG_RATIO; !CONFIG_SWIDTH; !CONFIG_ALIGN; !CONFIG_FORMAT; !CONFIG_CHANNELS; } /// Inter Processor Communication 0 pub mod IPC_NS { TASKS_SEND_0; TASKS_SEND_1; TASKS_SEND_2; TASKS_SEND_3; TASKS_SEND_4; TASKS_SEND_5; TASKS_SEND_6; TASKS_SEND_7; SUBSCRIBE_SEND_0; SUBSCRIBE_SEND_1; SUBSCRIBE_SEND_2; SUBSCRIBE_SEND_3; SUBSCRIBE_SEND_4; SUBSCRIBE_SEND_5; SUBSCRIBE_SEND_6; SUBSCRIBE_SEND_7; EVENTS_RECEIVE_0; EVENTS_RECEIVE_1; EVENTS_RECEIVE_2; EVENTS_RECEIVE_3; EVENTS_RECEIVE_4; EVENTS_RECEIVE_5; EVENTS_RECEIVE_6; EVENTS_RECEIVE_7; PUBLISH_RECEIVE_0; PUBLISH_RECEIVE_1; PUBLISH_RECEIVE_2; PUBLISH_RECEIVE_3; PUBLISH_RECEIVE_4; PUBLISH_RECEIVE_5; PUBLISH_RECEIVE_6; PUBLISH_RECEIVE_7; INTEN; INTENSET; INTENCLR; INTPEND; SEND_CNF_0; SEND_CNF_1; SEND_CNF_2; SEND_CNF_3; SEND_CNF_4; SEND_CNF_5; SEND_CNF_6; SEND_CNF_7; RECEIVE_CNF_0; RECEIVE_CNF_1; RECEIVE_CNF_2; RECEIVE_CNF_3; RECEIVE_CNF_4; RECEIVE_CNF_5; RECEIVE_CNF_6; RECEIVE_CNF_7; GPMEM_0; GPMEM_1; GPMEM_2; GPMEM_3; } /// Inter Processor Communication 1 pub mod IPC_S { !TASKS_SEND_0; !TASKS_SEND_1; !TASKS_SEND_2; !TASKS_SEND_3; !TASKS_SEND_4; !TASKS_SEND_5; !TASKS_SEND_6; !TASKS_SEND_7; !SUBSCRIBE_SEND_0; !SUBSCRIBE_SEND_1; !SUBSCRIBE_SEND_2; !SUBSCRIBE_SEND_3; !SUBSCRIBE_SEND_4; !SUBSCRIBE_SEND_5; !SUBSCRIBE_SEND_6; !SUBSCRIBE_SEND_7; !EVENTS_RECEIVE_0; !EVENTS_RECEIVE_1; !EVENTS_RECEIVE_2; !EVENTS_RECEIVE_3; !EVENTS_RECEIVE_4; !EVENTS_RECEIVE_5; !EVENTS_RECEIVE_6; !EVENTS_RECEIVE_7; !PUBLISH_RECEIVE_0; !PUBLISH_RECEIVE_1; !PUBLISH_RECEIVE_2; !PUBLISH_RECEIVE_3; !PUBLISH_RECEIVE_4; !PUBLISH_RECEIVE_5; !PUBLISH_RECEIVE_6; !PUBLISH_RECEIVE_7; !INTEN; !INTENSET; !INTENCLR; !INTPEND; !SEND_CNF_0; !SEND_CNF_1; !SEND_CNF_2; !SEND_CNF_3; !SEND_CNF_4; !SEND_CNF_5; !SEND_CNF_6; !SEND_CNF_7; !RECEIVE_CNF_0; !RECEIVE_CNF_1; !RECEIVE_CNF_2; !RECEIVE_CNF_3; !RECEIVE_CNF_4; !RECEIVE_CNF_5; !RECEIVE_CNF_6; !RECEIVE_CNF_7; !GPMEM_0; !GPMEM_1; !GPMEM_2; !GPMEM_3; } /// GPIO Tasks and Events 1 pub mod GPIOTE1_NS { TASKS_OUT_0; TASKS_OUT_1; TASKS_OUT_2; TASKS_OUT_3; TASKS_OUT_4; TASKS_OUT_5; TASKS_OUT_6; TASKS_OUT_7; TASKS_SET_0; TASKS_SET_1; TASKS_SET_2; TASKS_SET_3; TASKS_SET_4; TASKS_SET_5; TASKS_SET_6; TASKS_SET_7; TASKS_CLR_0; TASKS_CLR_1; TASKS_CLR_2; TASKS_CLR_3; TASKS_CLR_4; TASKS_CLR_5; TASKS_CLR_6; TASKS_CLR_7; SUBSCRIBE_OUT_0; SUBSCRIBE_OUT_1; SUBSCRIBE_OUT_2; SUBSCRIBE_OUT_3; SUBSCRIBE_OUT_4; SUBSCRIBE_OUT_5; SUBSCRIBE_OUT_6; SUBSCRIBE_OUT_7; SUBSCRIBE_SET_0; SUBSCRIBE_SET_1; SUBSCRIBE_SET_2; SUBSCRIBE_SET_3; SUBSCRIBE_SET_4; SUBSCRIBE_SET_5; SUBSCRIBE_SET_6; SUBSCRIBE_SET_7; SUBSCRIBE_CLR_0; SUBSCRIBE_CLR_1; SUBSCRIBE_CLR_2; SUBSCRIBE_CLR_3; SUBSCRIBE_CLR_4; SUBSCRIBE_CLR_5; SUBSCRIBE_CLR_6; SUBSCRIBE_CLR_7; EVENTS_IN_0; EVENTS_IN_1; EVENTS_IN_2; EVENTS_IN_3; EVENTS_IN_4; EVENTS_IN_5; EVENTS_IN_6; EVENTS_IN_7; EVENTS_PORT; PUBLISH_IN_0; PUBLISH_IN_1; PUBLISH_IN_2; PUBLISH_IN_3; PUBLISH_IN_4; PUBLISH_IN_5; PUBLISH_IN_6; PUBLISH_IN_7; PUBLISH_PORT; INTENSET; INTENCLR; CONFIG_0; CONFIG_1; CONFIG_2; CONFIG_3; CONFIG_4; CONFIG_5; CONFIG_6; CONFIG_7; } /// Key management unit 0 pub mod KMU_NS { TASKS_PUSH_KEYSLOT; EVENTS_KEYSLOT_PUSHED; EVENTS_KEYSLOT_REVOKED; EVENTS_KEYSLOT_ERROR; INTEN; INTENSET; INTENCLR; INTPEND; STATUS; SELECTKEYSLOT; } /// Key management unit 1 pub mod KMU_S { !TASKS_PUSH_KEYSLOT; !EVENTS_KEYSLOT_PUSHED; !EVENTS_KEYSLOT_REVOKED; !EVENTS_KEYSLOT_ERROR; !INTEN; !INTENSET; !INTENCLR; !INTPEND; !STATUS; !SELECTKEYSLOT; } /// Non-volatile memory controller 0 pub mod NVMC_NS { READY; READYNEXT; CONFIG; ERASEALL; ERASEPAGEPARTIALCFG; ICACHECNF; IHIT; IMISS; CONFIGNS; WRITEUICRNS; } /// Non-volatile memory controller 1 pub mod NVMC_S { !READY; !READYNEXT; !CONFIG; !ERASEALL; !ERASEPAGEPARTIALCFG; !ICACHECNF; !IHIT; !IMISS; !CONFIGNS; !WRITEUICRNS; } /// Volatile Memory controller 0 pub mod VMC_NS { RAM_0_POWER; RAM_1_POWER; RAM_2_POWER; RAM_3_POWER; RAM_4_POWER; RAM_5_POWER; RAM_6_POWER; RAM_7_POWER; RAM_0_POWERSET; RAM_1_POWERSET; RAM_2_POWERSET; RAM_3_POWERSET; RAM_4_POWERSET; RAM_5_POWERSET; RAM_6_POWERSET; RAM_7_POWERSET; RAM_0_POWERCLR; RAM_1_POWERCLR; RAM_2_POWERCLR; RAM_3_POWERCLR; RAM_4_POWERCLR; RAM_5_POWERCLR; RAM_6_POWERCLR; RAM_7_POWERCLR; } /// Volatile Memory controller 1 pub mod VMC_S { !RAM_0_POWER; !RAM_1_POWER; !RAM_2_POWER; !RAM_3_POWER; !RAM_4_POWER; !RAM_5_POWER; !RAM_6_POWER; !RAM_7_POWER; !RAM_0_POWERSET; !RAM_1_POWERSET; !RAM_2_POWERSET; !RAM_3_POWERSET; !RAM_4_POWERSET; !RAM_5_POWERSET; !RAM_6_POWERSET; !RAM_7_POWERSET; !RAM_0_POWERCLR; !RAM_1_POWERCLR; !RAM_2_POWERCLR; !RAM_3_POWERCLR; !RAM_4_POWERCLR; !RAM_5_POWERCLR; !RAM_6_POWERCLR; !RAM_7_POWERCLR; } /// CRYPTOCELL HOST_RGF interface pub mod CC_HOST_RGF_S { HOST_CRYPTOKEY_SEL; HOST_IOT_KPRTL_LOCK; HOST_IOT_KDR0; HOST_IOT_KDR1; HOST_IOT_KDR2; HOST_IOT_KDR3; HOST_IOT_LCS; } /// ARM TrustZone CryptoCell register interface pub mod CRYPTOCELL_S { ENABLE; } /// GPIO Port 0 pub mod P0_NS { OUT; OUTSET; OUTCLR; IN; DIR; DIRSET; DIRCLR; LATCH; DETECTMODE; DETECTMODE_SEC; PIN_CNF_0; PIN_CNF_1; PIN_CNF_2; PIN_CNF_3; PIN_CNF_4; PIN_CNF_5; PIN_CNF_6; PIN_CNF_7; PIN_CNF_8; PIN_CNF_9; PIN_CNF_10; PIN_CNF_11; PIN_CNF_12; PIN_CNF_13; PIN_CNF_14; PIN_CNF_15; PIN_CNF_16; PIN_CNF_17; PIN_CNF_18; PIN_CNF_19; PIN_CNF_20; PIN_CNF_21; PIN_CNF_22; PIN_CNF_23; PIN_CNF_24; PIN_CNF_25; PIN_CNF_26; PIN_CNF_27; PIN_CNF_28; PIN_CNF_29; PIN_CNF_30; PIN_CNF_31; } /// GPIO Port 1 pub mod P0_S { !OUT; !OUTSET; !OUTCLR; !IN; !DIR; !DIRSET; !DIRCLR; !LATCH; !DETECTMODE; !DETECTMODE_SEC; !PIN_CNF_0; !PIN_CNF_1; !PIN_CNF_2; !PIN_CNF_3; !PIN_CNF_4; !PIN_CNF_5; !PIN_CNF_6; !PIN_CNF_7; !PIN_CNF_8; !PIN_CNF_9; !PIN_CNF_10; !PIN_CNF_11; !PIN_CNF_12; !PIN_CNF_13; !PIN_CNF_14; !PIN_CNF_15; !PIN_CNF_16; !PIN_CNF_17; !PIN_CNF_18; !PIN_CNF_19; !PIN_CNF_20; !PIN_CNF_21; !PIN_CNF_22; !PIN_CNF_23; !PIN_CNF_24; !PIN_CNF_25; !PIN_CNF_26; !PIN_CNF_27; !PIN_CNF_28; !PIN_CNF_29; !PIN_CNF_30; !PIN_CNF_31; } } => { ... }; reg::tokens! { /// Defines an index of nrf9160 register tokens. pub macro nrf_reg_tokens; use macro drone_cortexm::map::cortexm_reg_tokens; super::inner; crate::reg; /// Factory Information Configuration Registers pub mod FICR_S { TRNG90B_BYTES; TRNG90B_RCCUTOFF; TRNG90B_APCUTOFF; TRNG90B_STARTUP; TRNG90B_ROSC1; TRNG90B_ROSC2; TRNG90B_ROSC3; TRNG90B_ROSC4; TRIMCNF_0_ADDR; TRIMCNF_1_ADDR; TRIMCNF_2_ADDR; TRIMCNF_3_ADDR; TRIMCNF_4_ADDR; TRIMCNF_5_ADDR; TRIMCNF_6_ADDR; TRIMCNF_7_ADDR; TRIMCNF_8_ADDR; TRIMCNF_9_ADDR; TRIMCNF_10_ADDR; TRIMCNF_11_ADDR; TRIMCNF_12_ADDR; TRIMCNF_13_ADDR; TRIMCNF_14_ADDR; TRIMCNF_15_ADDR; TRIMCNF_16_ADDR; TRIMCNF_17_ADDR; TRIMCNF_18_ADDR; TRIMCNF_19_ADDR; TRIMCNF_20_ADDR; TRIMCNF_21_ADDR; TRIMCNF_22_ADDR; TRIMCNF_23_ADDR; TRIMCNF_24_ADDR; TRIMCNF_25_ADDR; TRIMCNF_26_ADDR; TRIMCNF_27_ADDR; TRIMCNF_28_ADDR; TRIMCNF_29_ADDR; TRIMCNF_30_ADDR; TRIMCNF_31_ADDR; TRIMCNF_32_ADDR; TRIMCNF_33_ADDR; TRIMCNF_34_ADDR; TRIMCNF_35_ADDR; TRIMCNF_36_ADDR; TRIMCNF_37_ADDR; TRIMCNF_38_ADDR; TRIMCNF_39_ADDR; TRIMCNF_40_ADDR; TRIMCNF_41_ADDR; TRIMCNF_42_ADDR; TRIMCNF_43_ADDR; TRIMCNF_44_ADDR; TRIMCNF_45_ADDR; TRIMCNF_46_ADDR; TRIMCNF_47_ADDR; TRIMCNF_48_ADDR; TRIMCNF_49_ADDR; TRIMCNF_50_ADDR; TRIMCNF_51_ADDR; TRIMCNF_52_ADDR; TRIMCNF_53_ADDR; TRIMCNF_54_ADDR; TRIMCNF_55_ADDR; TRIMCNF_56_ADDR; TRIMCNF_57_ADDR; TRIMCNF_58_ADDR; TRIMCNF_59_ADDR; TRIMCNF_60_ADDR; TRIMCNF_61_ADDR; TRIMCNF_62_ADDR; TRIMCNF_63_ADDR; TRIMCNF_64_ADDR; TRIMCNF_65_ADDR; TRIMCNF_66_ADDR; TRIMCNF_67_ADDR; TRIMCNF_68_ADDR; TRIMCNF_69_ADDR; TRIMCNF_70_ADDR; TRIMCNF_71_ADDR; TRIMCNF_72_ADDR; TRIMCNF_73_ADDR; TRIMCNF_74_ADDR; TRIMCNF_75_ADDR; TRIMCNF_76_ADDR; TRIMCNF_77_ADDR; TRIMCNF_78_ADDR; TRIMCNF_79_ADDR; TRIMCNF_80_ADDR; TRIMCNF_81_ADDR; TRIMCNF_82_ADDR; TRIMCNF_83_ADDR; TRIMCNF_84_ADDR; TRIMCNF_85_ADDR; TRIMCNF_86_ADDR; TRIMCNF_87_ADDR; TRIMCNF_88_ADDR; TRIMCNF_89_ADDR; TRIMCNF_90_ADDR; TRIMCNF_91_ADDR; TRIMCNF_92_ADDR; TRIMCNF_93_ADDR; TRIMCNF_94_ADDR; TRIMCNF_95_ADDR; TRIMCNF_96_ADDR; TRIMCNF_97_ADDR; TRIMCNF_98_ADDR; TRIMCNF_99_ADDR; TRIMCNF_100_ADDR; TRIMCNF_101_ADDR; TRIMCNF_102_ADDR; TRIMCNF_103_ADDR; TRIMCNF_104_ADDR; TRIMCNF_105_ADDR; TRIMCNF_106_ADDR; TRIMCNF_107_ADDR; TRIMCNF_108_ADDR; TRIMCNF_109_ADDR; TRIMCNF_110_ADDR; TRIMCNF_111_ADDR; TRIMCNF_112_ADDR; TRIMCNF_113_ADDR; TRIMCNF_114_ADDR; TRIMCNF_115_ADDR; TRIMCNF_116_ADDR; TRIMCNF_117_ADDR; TRIMCNF_118_ADDR; TRIMCNF_119_ADDR; TRIMCNF_120_ADDR; TRIMCNF_121_ADDR; TRIMCNF_122_ADDR; TRIMCNF_123_ADDR; TRIMCNF_124_ADDR; TRIMCNF_125_ADDR; TRIMCNF_126_ADDR; TRIMCNF_127_ADDR; TRIMCNF_128_ADDR; TRIMCNF_129_ADDR; TRIMCNF_130_ADDR; TRIMCNF_131_ADDR; TRIMCNF_132_ADDR; TRIMCNF_133_ADDR; TRIMCNF_134_ADDR; TRIMCNF_135_ADDR; TRIMCNF_136_ADDR; TRIMCNF_137_ADDR; TRIMCNF_138_ADDR; TRIMCNF_139_ADDR; TRIMCNF_140_ADDR; TRIMCNF_141_ADDR; TRIMCNF_142_ADDR; TRIMCNF_143_ADDR; TRIMCNF_144_ADDR; TRIMCNF_145_ADDR; TRIMCNF_146_ADDR; TRIMCNF_147_ADDR; TRIMCNF_148_ADDR; TRIMCNF_149_ADDR; TRIMCNF_150_ADDR; TRIMCNF_151_ADDR; TRIMCNF_152_ADDR; TRIMCNF_153_ADDR; TRIMCNF_154_ADDR; TRIMCNF_155_ADDR; TRIMCNF_156_ADDR; TRIMCNF_157_ADDR; TRIMCNF_158_ADDR; TRIMCNF_159_ADDR; TRIMCNF_160_ADDR; TRIMCNF_161_ADDR; TRIMCNF_162_ADDR; TRIMCNF_163_ADDR; TRIMCNF_164_ADDR; TRIMCNF_165_ADDR; TRIMCNF_166_ADDR; TRIMCNF_167_ADDR; TRIMCNF_168_ADDR; TRIMCNF_169_ADDR; TRIMCNF_170_ADDR; TRIMCNF_171_ADDR; TRIMCNF_172_ADDR; TRIMCNF_173_ADDR; TRIMCNF_174_ADDR; TRIMCNF_175_ADDR; TRIMCNF_176_ADDR; TRIMCNF_177_ADDR; TRIMCNF_178_ADDR; TRIMCNF_179_ADDR; TRIMCNF_180_ADDR; TRIMCNF_181_ADDR; TRIMCNF_182_ADDR; TRIMCNF_183_ADDR; TRIMCNF_184_ADDR; TRIMCNF_185_ADDR; TRIMCNF_186_ADDR; TRIMCNF_187_ADDR; TRIMCNF_188_ADDR; TRIMCNF_189_ADDR; TRIMCNF_190_ADDR; TRIMCNF_191_ADDR; TRIMCNF_192_ADDR; TRIMCNF_193_ADDR; TRIMCNF_194_ADDR; TRIMCNF_195_ADDR; TRIMCNF_196_ADDR; TRIMCNF_197_ADDR; TRIMCNF_198_ADDR; TRIMCNF_199_ADDR; TRIMCNF_200_ADDR; TRIMCNF_201_ADDR; TRIMCNF_202_ADDR; TRIMCNF_203_ADDR; TRIMCNF_204_ADDR; TRIMCNF_205_ADDR; TRIMCNF_206_ADDR; TRIMCNF_207_ADDR; TRIMCNF_208_ADDR; TRIMCNF_209_ADDR; TRIMCNF_210_ADDR; TRIMCNF_211_ADDR; TRIMCNF_212_ADDR; TRIMCNF_213_ADDR; TRIMCNF_214_ADDR; TRIMCNF_215_ADDR; TRIMCNF_216_ADDR; TRIMCNF_217_ADDR; TRIMCNF_218_ADDR; TRIMCNF_219_ADDR; TRIMCNF_220_ADDR; TRIMCNF_221_ADDR; TRIMCNF_222_ADDR; TRIMCNF_223_ADDR; TRIMCNF_224_ADDR; TRIMCNF_225_ADDR; TRIMCNF_226_ADDR; TRIMCNF_227_ADDR; TRIMCNF_228_ADDR; TRIMCNF_229_ADDR; TRIMCNF_230_ADDR; TRIMCNF_231_ADDR; TRIMCNF_232_ADDR; TRIMCNF_233_ADDR; TRIMCNF_234_ADDR; TRIMCNF_235_ADDR; TRIMCNF_236_ADDR; TRIMCNF_237_ADDR; TRIMCNF_238_ADDR; TRIMCNF_239_ADDR; TRIMCNF_240_ADDR; TRIMCNF_241_ADDR; TRIMCNF_242_ADDR; TRIMCNF_243_ADDR; TRIMCNF_244_ADDR; TRIMCNF_245_ADDR; TRIMCNF_246_ADDR; TRIMCNF_247_ADDR; TRIMCNF_248_ADDR; TRIMCNF_249_ADDR; TRIMCNF_250_ADDR; TRIMCNF_251_ADDR; TRIMCNF_252_ADDR; TRIMCNF_253_ADDR; TRIMCNF_254_ADDR; TRIMCNF_255_ADDR; TRIMCNF_0_DATA; TRIMCNF_1_DATA; TRIMCNF_2_DATA; TRIMCNF_3_DATA; TRIMCNF_4_DATA; TRIMCNF_5_DATA; TRIMCNF_6_DATA; TRIMCNF_7_DATA; TRIMCNF_8_DATA; TRIMCNF_9_DATA; TRIMCNF_10_DATA; TRIMCNF_11_DATA; TRIMCNF_12_DATA; TRIMCNF_13_DATA; TRIMCNF_14_DATA; TRIMCNF_15_DATA; TRIMCNF_16_DATA; TRIMCNF_17_DATA; TRIMCNF_18_DATA; TRIMCNF_19_DATA; TRIMCNF_20_DATA; TRIMCNF_21_DATA; TRIMCNF_22_DATA; TRIMCNF_23_DATA; TRIMCNF_24_DATA; TRIMCNF_25_DATA; TRIMCNF_26_DATA; TRIMCNF_27_DATA; TRIMCNF_28_DATA; TRIMCNF_29_DATA; TRIMCNF_30_DATA; TRIMCNF_31_DATA; TRIMCNF_32_DATA; TRIMCNF_33_DATA; TRIMCNF_34_DATA; TRIMCNF_35_DATA; TRIMCNF_36_DATA; TRIMCNF_37_DATA; TRIMCNF_38_DATA; TRIMCNF_39_DATA; TRIMCNF_40_DATA; TRIMCNF_41_DATA; TRIMCNF_42_DATA; TRIMCNF_43_DATA; TRIMCNF_44_DATA; TRIMCNF_45_DATA; TRIMCNF_46_DATA; TRIMCNF_47_DATA; TRIMCNF_48_DATA; TRIMCNF_49_DATA; TRIMCNF_50_DATA; TRIMCNF_51_DATA; TRIMCNF_52_DATA; TRIMCNF_53_DATA; TRIMCNF_54_DATA; TRIMCNF_55_DATA; TRIMCNF_56_DATA; TRIMCNF_57_DATA; TRIMCNF_58_DATA; TRIMCNF_59_DATA; TRIMCNF_60_DATA; TRIMCNF_61_DATA; TRIMCNF_62_DATA; TRIMCNF_63_DATA; TRIMCNF_64_DATA; TRIMCNF_65_DATA; TRIMCNF_66_DATA; TRIMCNF_67_DATA; TRIMCNF_68_DATA; TRIMCNF_69_DATA; TRIMCNF_70_DATA; TRIMCNF_71_DATA; TRIMCNF_72_DATA; TRIMCNF_73_DATA; TRIMCNF_74_DATA; TRIMCNF_75_DATA; TRIMCNF_76_DATA; TRIMCNF_77_DATA; TRIMCNF_78_DATA; TRIMCNF_79_DATA; TRIMCNF_80_DATA; TRIMCNF_81_DATA; TRIMCNF_82_DATA; TRIMCNF_83_DATA; TRIMCNF_84_DATA; TRIMCNF_85_DATA; TRIMCNF_86_DATA; TRIMCNF_87_DATA; TRIMCNF_88_DATA; TRIMCNF_89_DATA; TRIMCNF_90_DATA; TRIMCNF_91_DATA; TRIMCNF_92_DATA; TRIMCNF_93_DATA; TRIMCNF_94_DATA; TRIMCNF_95_DATA; TRIMCNF_96_DATA; TRIMCNF_97_DATA; TRIMCNF_98_DATA; TRIMCNF_99_DATA; TRIMCNF_100_DATA; TRIMCNF_101_DATA; TRIMCNF_102_DATA; TRIMCNF_103_DATA; TRIMCNF_104_DATA; TRIMCNF_105_DATA; TRIMCNF_106_DATA; TRIMCNF_107_DATA; TRIMCNF_108_DATA; TRIMCNF_109_DATA; TRIMCNF_110_DATA; TRIMCNF_111_DATA; TRIMCNF_112_DATA; TRIMCNF_113_DATA; TRIMCNF_114_DATA; TRIMCNF_115_DATA; TRIMCNF_116_DATA; TRIMCNF_117_DATA; TRIMCNF_118_DATA; TRIMCNF_119_DATA; TRIMCNF_120_DATA; TRIMCNF_121_DATA; TRIMCNF_122_DATA; TRIMCNF_123_DATA; TRIMCNF_124_DATA; TRIMCNF_125_DATA; TRIMCNF_126_DATA; TRIMCNF_127_DATA; TRIMCNF_128_DATA; TRIMCNF_129_DATA; TRIMCNF_130_DATA; TRIMCNF_131_DATA; TRIMCNF_132_DATA; TRIMCNF_133_DATA; TRIMCNF_134_DATA; TRIMCNF_135_DATA; TRIMCNF_136_DATA; TRIMCNF_137_DATA; TRIMCNF_138_DATA; TRIMCNF_139_DATA; TRIMCNF_140_DATA; TRIMCNF_141_DATA; TRIMCNF_142_DATA; TRIMCNF_143_DATA; TRIMCNF_144_DATA; TRIMCNF_145_DATA; TRIMCNF_146_DATA; TRIMCNF_147_DATA; TRIMCNF_148_DATA; TRIMCNF_149_DATA; TRIMCNF_150_DATA; TRIMCNF_151_DATA; TRIMCNF_152_DATA; TRIMCNF_153_DATA; TRIMCNF_154_DATA; TRIMCNF_155_DATA; TRIMCNF_156_DATA; TRIMCNF_157_DATA; TRIMCNF_158_DATA; TRIMCNF_159_DATA; TRIMCNF_160_DATA; TRIMCNF_161_DATA; TRIMCNF_162_DATA; TRIMCNF_163_DATA; TRIMCNF_164_DATA; TRIMCNF_165_DATA; TRIMCNF_166_DATA; TRIMCNF_167_DATA; TRIMCNF_168_DATA; TRIMCNF_169_DATA; TRIMCNF_170_DATA; TRIMCNF_171_DATA; TRIMCNF_172_DATA; TRIMCNF_173_DATA; TRIMCNF_174_DATA; TRIMCNF_175_DATA; TRIMCNF_176_DATA; TRIMCNF_177_DATA; TRIMCNF_178_DATA; TRIMCNF_179_DATA; TRIMCNF_180_DATA; TRIMCNF_181_DATA; TRIMCNF_182_DATA; TRIMCNF_183_DATA; TRIMCNF_184_DATA; TRIMCNF_185_DATA; TRIMCNF_186_DATA; TRIMCNF_187_DATA; TRIMCNF_188_DATA; TRIMCNF_189_DATA; TRIMCNF_190_DATA; TRIMCNF_191_DATA; TRIMCNF_192_DATA; TRIMCNF_193_DATA; TRIMCNF_194_DATA; TRIMCNF_195_DATA; TRIMCNF_196_DATA; TRIMCNF_197_DATA; TRIMCNF_198_DATA; TRIMCNF_199_DATA; TRIMCNF_200_DATA; TRIMCNF_201_DATA; TRIMCNF_202_DATA; TRIMCNF_203_DATA; TRIMCNF_204_DATA; TRIMCNF_205_DATA; TRIMCNF_206_DATA; TRIMCNF_207_DATA; TRIMCNF_208_DATA; TRIMCNF_209_DATA; TRIMCNF_210_DATA; TRIMCNF_211_DATA; TRIMCNF_212_DATA; TRIMCNF_213_DATA; TRIMCNF_214_DATA; TRIMCNF_215_DATA; TRIMCNF_216_DATA; TRIMCNF_217_DATA; TRIMCNF_218_DATA; TRIMCNF_219_DATA; TRIMCNF_220_DATA; TRIMCNF_221_DATA; TRIMCNF_222_DATA; TRIMCNF_223_DATA; TRIMCNF_224_DATA; TRIMCNF_225_DATA; TRIMCNF_226_DATA; TRIMCNF_227_DATA; TRIMCNF_228_DATA; TRIMCNF_229_DATA; TRIMCNF_230_DATA; TRIMCNF_231_DATA; TRIMCNF_232_DATA; TRIMCNF_233_DATA; TRIMCNF_234_DATA; TRIMCNF_235_DATA; TRIMCNF_236_DATA; TRIMCNF_237_DATA; TRIMCNF_238_DATA; TRIMCNF_239_DATA; TRIMCNF_240_DATA; TRIMCNF_241_DATA; TRIMCNF_242_DATA; TRIMCNF_243_DATA; TRIMCNF_244_DATA; TRIMCNF_245_DATA; TRIMCNF_246_DATA; TRIMCNF_247_DATA; TRIMCNF_248_DATA; TRIMCNF_249_DATA; TRIMCNF_250_DATA; TRIMCNF_251_DATA; TRIMCNF_252_DATA; TRIMCNF_253_DATA; TRIMCNF_254_DATA; TRIMCNF_255_DATA; INFO_DEVICEID_0; INFO_DEVICEID_1; INFO_PART; INFO_VARIANT; INFO_PACKAGE; INFO_RAM; INFO_FLASH; INFO_CODEPAGESIZE; INFO_CODESIZE; INFO_DEVICETYPE; } /// User information configuration registers User information configuration registers pub mod UICR_S { APPROTECT; XOSC32M; HFXOSRC; HFXOCNT; SECUREAPPROTECT; ERASEPROTECT; OTP_0; OTP_1; OTP_2; OTP_3; OTP_4; OTP_5; OTP_6; OTP_7; OTP_8; OTP_9; OTP_10; OTP_11; OTP_12; OTP_13; OTP_14; OTP_15; OTP_16; OTP_17; OTP_18; OTP_19; OTP_20; OTP_21; OTP_22; OTP_23; OTP_24; OTP_25; OTP_26; OTP_27; OTP_28; OTP_29; OTP_30; OTP_31; OTP_32; OTP_33; OTP_34; OTP_35; OTP_36; OTP_37; OTP_38; OTP_39; OTP_40; OTP_41; OTP_42; OTP_43; OTP_44; OTP_45; OTP_46; OTP_47; OTP_48; OTP_49; OTP_50; OTP_51; OTP_52; OTP_53; OTP_54; OTP_55; OTP_56; OTP_57; OTP_58; OTP_59; OTP_60; OTP_61; OTP_62; OTP_63; OTP_64; OTP_65; OTP_66; OTP_67; OTP_68; OTP_69; OTP_70; OTP_71; OTP_72; OTP_73; OTP_74; OTP_75; OTP_76; OTP_77; OTP_78; OTP_79; OTP_80; OTP_81; OTP_82; OTP_83; OTP_84; OTP_85; OTP_86; OTP_87; OTP_88; OTP_89; OTP_90; OTP_91; OTP_92; OTP_93; OTP_94; OTP_95; OTP_96; OTP_97; OTP_98; OTP_99; OTP_100; OTP_101; OTP_102; OTP_103; OTP_104; OTP_105; OTP_106; OTP_107; OTP_108; OTP_109; OTP_110; OTP_111; OTP_112; OTP_113; OTP_114; OTP_115; OTP_116; OTP_117; OTP_118; OTP_119; OTP_120; OTP_121; OTP_122; OTP_123; OTP_124; OTP_125; OTP_126; OTP_127; OTP_128; OTP_129; OTP_130; OTP_131; OTP_132; OTP_133; OTP_134; OTP_135; OTP_136; OTP_137; OTP_138; OTP_139; OTP_140; OTP_141; OTP_142; OTP_143; OTP_144; OTP_145; OTP_146; OTP_147; OTP_148; OTP_149; OTP_150; OTP_151; OTP_152; OTP_153; OTP_154; OTP_155; OTP_156; OTP_157; OTP_158; OTP_159; OTP_160; OTP_161; OTP_162; OTP_163; OTP_164; OTP_165; OTP_166; OTP_167; OTP_168; OTP_169; OTP_170; OTP_171; OTP_172; OTP_173; OTP_174; OTP_175; OTP_176; OTP_177; OTP_178; OTP_179; OTP_180; OTP_181; OTP_182; OTP_183; OTP_184; OTP_185; OTP_186; OTP_187; OTP_188; OTP_189; } /// Trace and debug control pub mod TAD_S { CLOCKSTART; CLOCKSTOP; ENABLE; TRACEPORTSPEED; PSEL_TRACECLK; PSEL_TRACEDATA0; PSEL_TRACEDATA1; PSEL_TRACEDATA2; PSEL_TRACEDATA3; } /// System protection unit pub mod SPU_S { EVENTS_RAMACCERR; EVENTS_FLASHACCERR; EVENTS_PERIPHACCERR; PUBLISH_RAMACCERR; PUBLISH_FLASHACCERR; PUBLISH_PERIPHACCERR; INTEN; INTENSET; INTENCLR; CAP; PERIPHID_0_PERM; PERIPHID_1_PERM; PERIPHID_2_PERM; PERIPHID_3_PERM; PERIPHID_4_PERM; PERIPHID_5_PERM; PERIPHID_6_PERM; PERIPHID_7_PERM; PERIPHID_8_PERM; PERIPHID_9_PERM; PERIPHID_10_PERM; PERIPHID_11_PERM; PERIPHID_12_PERM; PERIPHID_13_PERM; PERIPHID_14_PERM; PERIPHID_15_PERM; PERIPHID_16_PERM; PERIPHID_17_PERM; PERIPHID_18_PERM; PERIPHID_19_PERM; PERIPHID_20_PERM; PERIPHID_21_PERM; PERIPHID_22_PERM; PERIPHID_23_PERM; PERIPHID_24_PERM; PERIPHID_25_PERM; PERIPHID_26_PERM; PERIPHID_27_PERM; PERIPHID_28_PERM; PERIPHID_29_PERM; PERIPHID_30_PERM; PERIPHID_31_PERM; PERIPHID_32_PERM; PERIPHID_33_PERM; PERIPHID_34_PERM; PERIPHID_35_PERM; PERIPHID_36_PERM; PERIPHID_37_PERM; PERIPHID_38_PERM; PERIPHID_39_PERM; PERIPHID_40_PERM; PERIPHID_41_PERM; PERIPHID_42_PERM; PERIPHID_43_PERM; PERIPHID_44_PERM; PERIPHID_45_PERM; PERIPHID_46_PERM; PERIPHID_47_PERM; PERIPHID_48_PERM; PERIPHID_49_PERM; PERIPHID_50_PERM; PERIPHID_51_PERM; PERIPHID_52_PERM; PERIPHID_53_PERM; PERIPHID_54_PERM; PERIPHID_55_PERM; PERIPHID_56_PERM; PERIPHID_57_PERM; PERIPHID_58_PERM; PERIPHID_59_PERM; PERIPHID_60_PERM; PERIPHID_61_PERM; PERIPHID_62_PERM; PERIPHID_63_PERM; PERIPHID_64_PERM; PERIPHID_65_PERM; PERIPHID_66_PERM; RAMREGION_0_PERM; RAMREGION_1_PERM; RAMREGION_2_PERM; RAMREGION_3_PERM; RAMREGION_4_PERM; RAMREGION_5_PERM; RAMREGION_6_PERM; RAMREGION_7_PERM; RAMREGION_8_PERM; RAMREGION_9_PERM; RAMREGION_10_PERM; RAMREGION_11_PERM; RAMREGION_12_PERM; RAMREGION_13_PERM; RAMREGION_14_PERM; RAMREGION_15_PERM; RAMREGION_16_PERM; RAMREGION_17_PERM; RAMREGION_18_PERM; RAMREGION_19_PERM; RAMREGION_20_PERM; RAMREGION_21_PERM; RAMREGION_22_PERM; RAMREGION_23_PERM; RAMREGION_24_PERM; RAMREGION_25_PERM; RAMREGION_26_PERM; RAMREGION_27_PERM; RAMREGION_28_PERM; RAMREGION_29_PERM; RAMREGION_30_PERM; RAMREGION_31_PERM; FLASHREGION_0_PERM; FLASHREGION_1_PERM; FLASHREGION_2_PERM; FLASHREGION_3_PERM; FLASHREGION_4_PERM; FLASHREGION_5_PERM; FLASHREGION_6_PERM; FLASHREGION_7_PERM; FLASHREGION_8_PERM; FLASHREGION_9_PERM; FLASHREGION_10_PERM; FLASHREGION_11_PERM; FLASHREGION_12_PERM; FLASHREGION_13_PERM; FLASHREGION_14_PERM; FLASHREGION_15_PERM; FLASHREGION_16_PERM; FLASHREGION_17_PERM; FLASHREGION_18_PERM; FLASHREGION_19_PERM; FLASHREGION_20_PERM; FLASHREGION_21_PERM; FLASHREGION_22_PERM; FLASHREGION_23_PERM; FLASHREGION_24_PERM; FLASHREGION_25_PERM; FLASHREGION_26_PERM; FLASHREGION_27_PERM; FLASHREGION_28_PERM; FLASHREGION_29_PERM; FLASHREGION_30_PERM; FLASHREGION_31_PERM; RAMNSC_0_REGION; RAMNSC_1_REGION; RAMNSC_0_SIZE; RAMNSC_1_SIZE; FLASHNSC_0_REGION; FLASHNSC_1_REGION; FLASHNSC_0_SIZE; FLASHNSC_1_SIZE; GPIOPORT_0_PERM; GPIOPORT_0_LOCK; DPPI_0_PERM; DPPI_0_LOCK; EXTDOMAIN_0_PERM; } /// Voltage regulators control 0 pub mod REGULATORS_NS { SYSTEMOFF; DCDCEN; } /// Voltage regulators control 1 pub mod REGULATORS_S { !SYSTEMOFF; !DCDCEN; } /// Clock management 0 pub mod CLOCK_NS { TASKS_HFCLKSTART; TASKS_HFCLKSTOP; TASKS_LFCLKSTART; TASKS_LFCLKSTOP; SUBSCRIBE_HFCLKSTART; SUBSCRIBE_HFCLKSTOP; SUBSCRIBE_LFCLKSTART; SUBSCRIBE_LFCLKSTOP; EVENTS_HFCLKSTARTED; EVENTS_LFCLKSTARTED; PUBLISH_HFCLKSTARTED; PUBLISH_LFCLKSTARTED; INTEN; INTENSET; INTENCLR; INTPEND; HFCLKRUN; HFCLKSTAT; LFCLKRUN; LFCLKSTAT; LFCLKSRCCOPY; LFCLKSRC; } /// Clock management 1 pub mod CLOCK_S { !TASKS_HFCLKSTART; !TASKS_HFCLKSTOP; !TASKS_LFCLKSTART; !TASKS_LFCLKSTOP; !SUBSCRIBE_HFCLKSTART; !SUBSCRIBE_HFCLKSTOP; !SUBSCRIBE_LFCLKSTART; !SUBSCRIBE_LFCLKSTOP; !EVENTS_HFCLKSTARTED; !EVENTS_LFCLKSTARTED; !PUBLISH_HFCLKSTARTED; !PUBLISH_LFCLKSTARTED; !INTEN; !INTENSET; !INTENCLR; !INTPEND; !HFCLKRUN; !HFCLKSTAT; !LFCLKRUN; !LFCLKSTAT; !LFCLKSRCCOPY; !LFCLKSRC; } /// Power control 0 pub mod POWER_NS { !INTEN; !INTENSET; !INTENCLR; TASKS_CONSTLAT; TASKS_LOWPWR; SUBSCRIBE_CONSTLAT; SUBSCRIBE_LOWPWR; EVENTS_POFWARN; EVENTS_SLEEPENTER; EVENTS_SLEEPEXIT; PUBLISH_POFWARN; PUBLISH_SLEEPENTER; PUBLISH_SLEEPEXIT; RESETREAS; POWERSTATUS; GPREGRET_0; GPREGRET_1; } /// Power control 1 pub mod POWER_S { !INTEN; !INTENSET; !INTENCLR; !TASKS_CONSTLAT; !TASKS_LOWPWR; !SUBSCRIBE_CONSTLAT; !SUBSCRIBE_LOWPWR; !EVENTS_POFWARN; !EVENTS_SLEEPENTER; !EVENTS_SLEEPEXIT; !PUBLISH_POFWARN; !PUBLISH_SLEEPENTER; !PUBLISH_SLEEPEXIT; !RESETREAS; !POWERSTATUS; !GPREGRET_0; !GPREGRET_1; } /// Control access port pub mod CTRL_AP_PERI_S { ERASEPROTECT_LOCK; ERASEPROTECT_DISABLE; MAILBOX_RXDATA; MAILBOX_RXSTATUS; MAILBOX_TXDATA; MAILBOX_TXSTATUS; } /// Serial Peripheral Interface Master with EasyDMA 0 pub mod SPIM0_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 1 pub mod SPIM0_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 0 pub mod TWIM0_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 pub mod TWIS0_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 1 pub mod TWIM0_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 pub mod TWIS0_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 0 pub mod SPIS0_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 0 pub mod UARTE0_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 1 pub mod SPIS0_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 1 pub mod UARTE0_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// Serial Peripheral Interface Master with EasyDMA 2 pub mod SPIM1_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 3 pub mod SPIM1_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 2 pub mod TWIM1_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 2 pub mod TWIS1_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 3 pub mod TWIM1_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 3 pub mod TWIS1_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 2 pub mod SPIS1_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 2 pub mod UARTE1_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 3 pub mod SPIS1_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 3 pub mod UARTE1_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// Serial Peripheral Interface Master with EasyDMA 4 pub mod SPIM2_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 5 pub mod SPIM2_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 4 pub mod TWIM2_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 4 pub mod TWIS2_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 5 pub mod TWIM2_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 5 pub mod TWIS2_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 4 pub mod SPIS2_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 4 pub mod UARTE2_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 5 pub mod SPIS2_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 5 pub mod UARTE2_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// Serial Peripheral Interface Master with EasyDMA 6 pub mod SPIM3_NS { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_SUSPEND; SUBSCRIBE_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; PUBLISH_STOPPED; PUBLISH_ENDRX; PUBLISH_END; PUBLISH_ENDTX; PUBLISH_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// Serial Peripheral Interface Master with EasyDMA 7 pub mod SPIM3_S { !TASKS_START; !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_ENDRX; !EVENTS_END; !EVENTS_ENDTX; !EVENTS_STARTED; !PUBLISH_STOPPED; !PUBLISH_ENDRX; !PUBLISH_END; !PUBLISH_ENDTX; !PUBLISH_STARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 6 pub mod TWIM3_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; SUBSCRIBE_STARTRX; SUBSCRIBE_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; PUBLISH_ERROR; PUBLISH_SUSPENDED; PUBLISH_TXSTARTED; PUBLISH_LASTRX; PUBLISH_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 6 pub mod TWIS3_NS { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; SUBSCRIBE_PREPARERX; SUBSCRIBE_PREPARETX; EVENTS_WRITE; EVENTS_READ; PUBLISH_WRITE; PUBLISH_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Master Interface with EasyDMA 7 pub mod TWIM3_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !EVENTS_TXSTARTED; !EVENTS_LASTRX; !EVENTS_LASTTX; !PUBLISH_ERROR; !PUBLISH_SUSPENDED; !PUBLISH_TXSTARTED; !PUBLISH_LASTRX; !PUBLISH_LASTTX; !INTEN; !ERRORSRC; !ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 7 pub mod TWIS3_S { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !SUBSCRIBE_STOP; !SUBSCRIBE_SUSPEND; !SUBSCRIBE_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !PUBLISH_STOPPED; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; !TASKS_PREPARERX; !TASKS_PREPARETX; !SUBSCRIBE_PREPARERX; !SUBSCRIBE_PREPARETX; !EVENTS_WRITE; !EVENTS_READ; !PUBLISH_WRITE; !PUBLISH_READ; !ERRORSRC; !MATCH; !CONFIG; } /// SPI Slave 6 pub mod SPIS3_NS { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; SUBSCRIBE_ACQUIRE; SUBSCRIBE_RELEASE; EVENTS_ACQUIRED; PUBLISH_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// UART with EasyDMA 6 pub mod UARTE3_NS { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; TASKS_STOPRX; TASKS_STOPTX; TASKS_FLUSHRX; SUBSCRIBE_STOPRX; SUBSCRIBE_STOPTX; SUBSCRIBE_FLUSHRX; EVENTS_CTS; EVENTS_RXDRDY; EVENTS_TXDRDY; EVENTS_RXTO; EVENTS_TXSTOPPED; PUBLISH_CTS; PUBLISH_RXDRDY; PUBLISH_TXDRDY; PUBLISH_RXTO; PUBLISH_TXSTOPPED; ERRORSRC; CONFIG; } /// SPI Slave 7 pub mod SPIS3_S { !EVENTS_END; !EVENTS_ENDRX; !PUBLISH_END; !PUBLISH_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; !TASKS_ACQUIRE; !TASKS_RELEASE; !SUBSCRIBE_ACQUIRE; !SUBSCRIBE_RELEASE; !EVENTS_ACQUIRED; !PUBLISH_ACQUIRED; !SEMSTAT; !STATUS; !DEF; !PSEL_CSN; } /// UART with EasyDMA 7 pub mod UARTE3_S { !EVENTS_NCTS; !EVENTS_ENDRX; !EVENTS_ENDTX; !EVENTS_RXSTARTED; !PUBLISH_NCTS; !PUBLISH_ENDRX; !PUBLISH_ENDTX; !PUBLISH_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !BAUDRATE; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_RTS; !PSEL_TXD; !PSEL_CTS; !PSEL_RXD; !TASKS_STARTRX; !TASKS_STARTTX; !SUBSCRIBE_STARTRX; !SUBSCRIBE_STARTTX; !EVENTS_ERROR; !EVENTS_TXSTARTED; !PUBLISH_ERROR; !PUBLISH_TXSTARTED; !INTEN; !TASKS_STOPRX; !TASKS_STOPTX; !TASKS_FLUSHRX; !SUBSCRIBE_STOPRX; !SUBSCRIBE_STOPTX; !SUBSCRIBE_FLUSHRX; !EVENTS_CTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_RXTO; !EVENTS_TXSTOPPED; !PUBLISH_CTS; !PUBLISH_RXDRDY; !PUBLISH_TXDRDY; !PUBLISH_RXTO; !PUBLISH_TXSTOPPED; !ERRORSRC; !CONFIG; } /// GPIO Tasks and Events 0 pub mod GPIOTE0_S { TASKS_OUT_0; TASKS_OUT_1; TASKS_OUT_2; TASKS_OUT_3; TASKS_OUT_4; TASKS_OUT_5; TASKS_OUT_6; TASKS_OUT_7; TASKS_SET_0; TASKS_SET_1; TASKS_SET_2; TASKS_SET_3; TASKS_SET_4; TASKS_SET_5; TASKS_SET_6; TASKS_SET_7; TASKS_CLR_0; TASKS_CLR_1; TASKS_CLR_2; TASKS_CLR_3; TASKS_CLR_4; TASKS_CLR_5; TASKS_CLR_6; TASKS_CLR_7; SUBSCRIBE_OUT_0; SUBSCRIBE_OUT_1; SUBSCRIBE_OUT_2; SUBSCRIBE_OUT_3; SUBSCRIBE_OUT_4; SUBSCRIBE_OUT_5; SUBSCRIBE_OUT_6; SUBSCRIBE_OUT_7; SUBSCRIBE_SET_0; SUBSCRIBE_SET_1; SUBSCRIBE_SET_2; SUBSCRIBE_SET_3; SUBSCRIBE_SET_4; SUBSCRIBE_SET_5; SUBSCRIBE_SET_6; SUBSCRIBE_SET_7; SUBSCRIBE_CLR_0; SUBSCRIBE_CLR_1; SUBSCRIBE_CLR_2; SUBSCRIBE_CLR_3; SUBSCRIBE_CLR_4; SUBSCRIBE_CLR_5; SUBSCRIBE_CLR_6; SUBSCRIBE_CLR_7; EVENTS_IN_0; EVENTS_IN_1; EVENTS_IN_2; EVENTS_IN_3; EVENTS_IN_4; EVENTS_IN_5; EVENTS_IN_6; EVENTS_IN_7; EVENTS_PORT; PUBLISH_IN_0; PUBLISH_IN_1; PUBLISH_IN_2; PUBLISH_IN_3; PUBLISH_IN_4; PUBLISH_IN_5; PUBLISH_IN_6; PUBLISH_IN_7; PUBLISH_PORT; INTENSET; INTENCLR; CONFIG_0; CONFIG_1; CONFIG_2; CONFIG_3; CONFIG_4; CONFIG_5; CONFIG_6; CONFIG_7; } /// Analog to Digital Converter 0 pub mod SAADC_NS { TASKS_START; TASKS_SAMPLE; TASKS_STOP; TASKS_CALIBRATEOFFSET; SUBSCRIBE_START; SUBSCRIBE_SAMPLE; SUBSCRIBE_STOP; SUBSCRIBE_CALIBRATEOFFSET; EVENTS_STARTED; EVENTS_END; EVENTS_DONE; EVENTS_RESULTDONE; EVENTS_CALIBRATEDONE; EVENTS_STOPPED; PUBLISH_STARTED; PUBLISH_END; PUBLISH_DONE; PUBLISH_RESULTDONE; PUBLISH_CALIBRATEDONE; PUBLISH_STOPPED; INTEN; INTENSET; INTENCLR; STATUS; ENABLE; RESOLUTION; OVERSAMPLE; SAMPLERATE; RESULT_PTR; RESULT_MAXCNT; RESULT_AMOUNT; CH_0_PSELP; CH_1_PSELP; CH_2_PSELP; CH_3_PSELP; CH_4_PSELP; CH_5_PSELP; CH_6_PSELP; CH_7_PSELP; CH_0_PSELN; CH_1_PSELN; CH_2_PSELN; CH_3_PSELN; CH_4_PSELN; CH_5_PSELN; CH_6_PSELN; CH_7_PSELN; CH_0_CONFIG; CH_1_CONFIG; CH_2_CONFIG; CH_3_CONFIG; CH_4_CONFIG; CH_5_CONFIG; CH_6_CONFIG; CH_7_CONFIG; CH_0_LIMIT; CH_1_LIMIT; CH_2_LIMIT; CH_3_LIMIT; CH_4_LIMIT; CH_5_LIMIT; CH_6_LIMIT; CH_7_LIMIT; PUBLISH_CH_0_LIMITH; PUBLISH_CH_1_LIMITH; PUBLISH_CH_2_LIMITH; PUBLISH_CH_3_LIMITH; PUBLISH_CH_4_LIMITH; PUBLISH_CH_5_LIMITH; PUBLISH_CH_6_LIMITH; PUBLISH_CH_7_LIMITH; PUBLISH_CH_0_LIMITL; PUBLISH_CH_1_LIMITL; PUBLISH_CH_2_LIMITL; PUBLISH_CH_3_LIMITL; PUBLISH_CH_4_LIMITL; PUBLISH_CH_5_LIMITL; PUBLISH_CH_6_LIMITL; PUBLISH_CH_7_LIMITL; EVENTS_CH_0_LIMITH; EVENTS_CH_1_LIMITH; EVENTS_CH_2_LIMITH; EVENTS_CH_3_LIMITH; EVENTS_CH_4_LIMITH; EVENTS_CH_5_LIMITH; EVENTS_CH_6_LIMITH; EVENTS_CH_7_LIMITH; EVENTS_CH_0_LIMITL; EVENTS_CH_1_LIMITL; EVENTS_CH_2_LIMITL; EVENTS_CH_3_LIMITL; EVENTS_CH_4_LIMITL; EVENTS_CH_5_LIMITL; EVENTS_CH_6_LIMITL; EVENTS_CH_7_LIMITL; } /// Analog to Digital Converter 1 pub mod SAADC_S { !TASKS_START; !TASKS_SAMPLE; !TASKS_STOP; !TASKS_CALIBRATEOFFSET; !SUBSCRIBE_START; !SUBSCRIBE_SAMPLE; !SUBSCRIBE_STOP; !SUBSCRIBE_CALIBRATEOFFSET; !EVENTS_STARTED; !EVENTS_END; !EVENTS_DONE; !EVENTS_RESULTDONE; !EVENTS_CALIBRATEDONE; !EVENTS_STOPPED; !PUBLISH_STARTED; !PUBLISH_END; !PUBLISH_DONE; !PUBLISH_RESULTDONE; !PUBLISH_CALIBRATEDONE; !PUBLISH_STOPPED; !INTEN; !INTENSET; !INTENCLR; !STATUS; !ENABLE; !RESOLUTION; !OVERSAMPLE; !SAMPLERATE; !RESULT_PTR; !RESULT_MAXCNT; !RESULT_AMOUNT; !CH_0_PSELP; !CH_1_PSELP; !CH_2_PSELP; !CH_3_PSELP; !CH_4_PSELP; !CH_5_PSELP; !CH_6_PSELP; !CH_7_PSELP; !CH_0_PSELN; !CH_1_PSELN; !CH_2_PSELN; !CH_3_PSELN; !CH_4_PSELN; !CH_5_PSELN; !CH_6_PSELN; !CH_7_PSELN; !CH_0_CONFIG; !CH_1_CONFIG; !CH_2_CONFIG; !CH_3_CONFIG; !CH_4_CONFIG; !CH_5_CONFIG; !CH_6_CONFIG; !CH_7_CONFIG; !CH_0_LIMIT; !CH_1_LIMIT; !CH_2_LIMIT; !CH_3_LIMIT; !CH_4_LIMIT; !CH_5_LIMIT; !CH_6_LIMIT; !CH_7_LIMIT; !PUBLISH_CH_0_LIMITH; !PUBLISH_CH_1_LIMITH; !PUBLISH_CH_2_LIMITH; !PUBLISH_CH_3_LIMITH; !PUBLISH_CH_4_LIMITH; !PUBLISH_CH_5_LIMITH; !PUBLISH_CH_6_LIMITH; !PUBLISH_CH_7_LIMITH; !PUBLISH_CH_0_LIMITL; !PUBLISH_CH_1_LIMITL; !PUBLISH_CH_2_LIMITL; !PUBLISH_CH_3_LIMITL; !PUBLISH_CH_4_LIMITL; !PUBLISH_CH_5_LIMITL; !PUBLISH_CH_6_LIMITL; !PUBLISH_CH_7_LIMITL; !EVENTS_CH_0_LIMITH; !EVENTS_CH_1_LIMITH; !EVENTS_CH_2_LIMITH; !EVENTS_CH_3_LIMITH; !EVENTS_CH_4_LIMITH; !EVENTS_CH_5_LIMITH; !EVENTS_CH_6_LIMITH; !EVENTS_CH_7_LIMITH; !EVENTS_CH_0_LIMITL; !EVENTS_CH_1_LIMITL; !EVENTS_CH_2_LIMITL; !EVENTS_CH_3_LIMITL; !EVENTS_CH_4_LIMITL; !EVENTS_CH_5_LIMITL; !EVENTS_CH_6_LIMITL; !EVENTS_CH_7_LIMITL; } /// Timer/Counter 0 pub mod TIMER0_NS { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_COUNT; SUBSCRIBE_CLEAR; SUBSCRIBE_SHUTDOWN; SUBSCRIBE_CAPTURE_0; SUBSCRIBE_CAPTURE_1; SUBSCRIBE_CAPTURE_2; SUBSCRIBE_CAPTURE_3; SUBSCRIBE_CAPTURE_4; SUBSCRIBE_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; PUBLISH_COMPARE_4; PUBLISH_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; ONESHOTEN_0; ONESHOTEN_1; ONESHOTEN_2; ONESHOTEN_3; ONESHOTEN_4; ONESHOTEN_5; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 1 pub mod TIMER0_S { !TASKS_START; !TASKS_STOP; !TASKS_COUNT; !TASKS_CLEAR; !TASKS_SHUTDOWN; !TASKS_CAPTURE_0; !TASKS_CAPTURE_1; !TASKS_CAPTURE_2; !TASKS_CAPTURE_3; !TASKS_CAPTURE_4; !TASKS_CAPTURE_5; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_COUNT; !SUBSCRIBE_CLEAR; !SUBSCRIBE_SHUTDOWN; !SUBSCRIBE_CAPTURE_0; !SUBSCRIBE_CAPTURE_1; !SUBSCRIBE_CAPTURE_2; !SUBSCRIBE_CAPTURE_3; !SUBSCRIBE_CAPTURE_4; !SUBSCRIBE_CAPTURE_5; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !EVENTS_COMPARE_4; !EVENTS_COMPARE_5; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !PUBLISH_COMPARE_4; !PUBLISH_COMPARE_5; !SHORTS; !INTENSET; !INTENCLR; !MODE; !BITMODE; !PRESCALER; !ONESHOTEN_0; !ONESHOTEN_1; !ONESHOTEN_2; !ONESHOTEN_3; !ONESHOTEN_4; !ONESHOTEN_5; !CC_0; !CC_1; !CC_2; !CC_3; !CC_4; !CC_5; } /// Timer/Counter 2 pub mod TIMER1_NS { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_COUNT; SUBSCRIBE_CLEAR; SUBSCRIBE_SHUTDOWN; SUBSCRIBE_CAPTURE_0; SUBSCRIBE_CAPTURE_1; SUBSCRIBE_CAPTURE_2; SUBSCRIBE_CAPTURE_3; SUBSCRIBE_CAPTURE_4; SUBSCRIBE_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; PUBLISH_COMPARE_4; PUBLISH_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; ONESHOTEN_0; ONESHOTEN_1; ONESHOTEN_2; ONESHOTEN_3; ONESHOTEN_4; ONESHOTEN_5; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 3 pub mod TIMER1_S { !TASKS_START; !TASKS_STOP; !TASKS_COUNT; !TASKS_CLEAR; !TASKS_SHUTDOWN; !TASKS_CAPTURE_0; !TASKS_CAPTURE_1; !TASKS_CAPTURE_2; !TASKS_CAPTURE_3; !TASKS_CAPTURE_4; !TASKS_CAPTURE_5; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_COUNT; !SUBSCRIBE_CLEAR; !SUBSCRIBE_SHUTDOWN; !SUBSCRIBE_CAPTURE_0; !SUBSCRIBE_CAPTURE_1; !SUBSCRIBE_CAPTURE_2; !SUBSCRIBE_CAPTURE_3; !SUBSCRIBE_CAPTURE_4; !SUBSCRIBE_CAPTURE_5; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !EVENTS_COMPARE_4; !EVENTS_COMPARE_5; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !PUBLISH_COMPARE_4; !PUBLISH_COMPARE_5; !SHORTS; !INTENSET; !INTENCLR; !MODE; !BITMODE; !PRESCALER; !ONESHOTEN_0; !ONESHOTEN_1; !ONESHOTEN_2; !ONESHOTEN_3; !ONESHOTEN_4; !ONESHOTEN_5; !CC_0; !CC_1; !CC_2; !CC_3; !CC_4; !CC_5; } /// Timer/Counter 4 pub mod TIMER2_NS { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_COUNT; SUBSCRIBE_CLEAR; SUBSCRIBE_SHUTDOWN; SUBSCRIBE_CAPTURE_0; SUBSCRIBE_CAPTURE_1; SUBSCRIBE_CAPTURE_2; SUBSCRIBE_CAPTURE_3; SUBSCRIBE_CAPTURE_4; SUBSCRIBE_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; PUBLISH_COMPARE_4; PUBLISH_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; ONESHOTEN_0; ONESHOTEN_1; ONESHOTEN_2; ONESHOTEN_3; ONESHOTEN_4; ONESHOTEN_5; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 5 pub mod TIMER2_S { !TASKS_START; !TASKS_STOP; !TASKS_COUNT; !TASKS_CLEAR; !TASKS_SHUTDOWN; !TASKS_CAPTURE_0; !TASKS_CAPTURE_1; !TASKS_CAPTURE_2; !TASKS_CAPTURE_3; !TASKS_CAPTURE_4; !TASKS_CAPTURE_5; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_COUNT; !SUBSCRIBE_CLEAR; !SUBSCRIBE_SHUTDOWN; !SUBSCRIBE_CAPTURE_0; !SUBSCRIBE_CAPTURE_1; !SUBSCRIBE_CAPTURE_2; !SUBSCRIBE_CAPTURE_3; !SUBSCRIBE_CAPTURE_4; !SUBSCRIBE_CAPTURE_5; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !EVENTS_COMPARE_4; !EVENTS_COMPARE_5; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !PUBLISH_COMPARE_4; !PUBLISH_COMPARE_5; !SHORTS; !INTENSET; !INTENCLR; !MODE; !BITMODE; !PRESCALER; !ONESHOTEN_0; !ONESHOTEN_1; !ONESHOTEN_2; !ONESHOTEN_3; !ONESHOTEN_4; !ONESHOTEN_5; !CC_0; !CC_1; !CC_2; !CC_3; !CC_4; !CC_5; } /// Real-time counter 0 pub mod RTC0_NS { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_CLEAR; SUBSCRIBE_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; PUBLISH_TICK; PUBLISH_OVRFLW; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Real-time counter 1 pub mod RTC0_S { !TASKS_START; !TASKS_STOP; !TASKS_CLEAR; !TASKS_TRIGOVRFLW; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_CLEAR; !SUBSCRIBE_TRIGOVRFLW; !EVENTS_TICK; !EVENTS_OVRFLW; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !PUBLISH_TICK; !PUBLISH_OVRFLW; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !INTENSET; !INTENCLR; !EVTEN; !EVTENSET; !EVTENCLR; !COUNTER; !PRESCALER; !CC_0; !CC_1; !CC_2; !CC_3; } /// Real-time counter 2 pub mod RTC1_NS { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; SUBSCRIBE_START; SUBSCRIBE_STOP; SUBSCRIBE_CLEAR; SUBSCRIBE_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; PUBLISH_TICK; PUBLISH_OVRFLW; PUBLISH_COMPARE_0; PUBLISH_COMPARE_1; PUBLISH_COMPARE_2; PUBLISH_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Real-time counter 3 pub mod RTC1_S { !TASKS_START; !TASKS_STOP; !TASKS_CLEAR; !TASKS_TRIGOVRFLW; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !SUBSCRIBE_CLEAR; !SUBSCRIBE_TRIGOVRFLW; !EVENTS_TICK; !EVENTS_OVRFLW; !EVENTS_COMPARE_0; !EVENTS_COMPARE_1; !EVENTS_COMPARE_2; !EVENTS_COMPARE_3; !PUBLISH_TICK; !PUBLISH_OVRFLW; !PUBLISH_COMPARE_0; !PUBLISH_COMPARE_1; !PUBLISH_COMPARE_2; !PUBLISH_COMPARE_3; !INTENSET; !INTENCLR; !EVTEN; !EVTENSET; !EVTENCLR; !COUNTER; !PRESCALER; !CC_0; !CC_1; !CC_2; !CC_3; } /// Distributed Programmable Peripheral Interconnect Controller 0 pub mod DPPIC_NS { CHEN; CHENSET; CHENCLR; CHG_0; CHG_1; CHG_2; CHG_3; CHG_4; CHG_5; SUBSCRIBE_CHG_0_EN; SUBSCRIBE_CHG_1_EN; SUBSCRIBE_CHG_2_EN; SUBSCRIBE_CHG_3_EN; SUBSCRIBE_CHG_4_EN; SUBSCRIBE_CHG_5_EN; SUBSCRIBE_CHG_0_DIS; SUBSCRIBE_CHG_1_DIS; SUBSCRIBE_CHG_2_DIS; SUBSCRIBE_CHG_3_DIS; SUBSCRIBE_CHG_4_DIS; SUBSCRIBE_CHG_5_DIS; TASKS_CHG_0_EN; TASKS_CHG_1_EN; TASKS_CHG_2_EN; TASKS_CHG_3_EN; TASKS_CHG_4_EN; TASKS_CHG_5_EN; TASKS_CHG_0_DIS; TASKS_CHG_1_DIS; TASKS_CHG_2_DIS; TASKS_CHG_3_DIS; TASKS_CHG_4_DIS; TASKS_CHG_5_DIS; } /// Distributed Programmable Peripheral Interconnect Controller 1 pub mod DPPIC_S { !CHEN; !CHENSET; !CHENCLR; !CHG_0; !CHG_1; !CHG_2; !CHG_3; !CHG_4; !CHG_5; !SUBSCRIBE_CHG_0_EN; !SUBSCRIBE_CHG_1_EN; !SUBSCRIBE_CHG_2_EN; !SUBSCRIBE_CHG_3_EN; !SUBSCRIBE_CHG_4_EN; !SUBSCRIBE_CHG_5_EN; !SUBSCRIBE_CHG_0_DIS; !SUBSCRIBE_CHG_1_DIS; !SUBSCRIBE_CHG_2_DIS; !SUBSCRIBE_CHG_3_DIS; !SUBSCRIBE_CHG_4_DIS; !SUBSCRIBE_CHG_5_DIS; !TASKS_CHG_0_EN; !TASKS_CHG_1_EN; !TASKS_CHG_2_EN; !TASKS_CHG_3_EN; !TASKS_CHG_4_EN; !TASKS_CHG_5_EN; !TASKS_CHG_0_DIS; !TASKS_CHG_1_DIS; !TASKS_CHG_2_DIS; !TASKS_CHG_3_DIS; !TASKS_CHG_4_DIS; !TASKS_CHG_5_DIS; } /// Watchdog Timer 0 pub mod WDT_NS { TASKS_START; SUBSCRIBE_START; EVENTS_TIMEOUT; PUBLISH_TIMEOUT; INTENSET; INTENCLR; RUNSTATUS; REQSTATUS; CRV; RREN; CONFIG; RR_0; RR_1; RR_2; RR_3; RR_4; RR_5; RR_6; RR_7; } /// Watchdog Timer 1 pub mod WDT_S { !TASKS_START; !SUBSCRIBE_START; !EVENTS_TIMEOUT; !PUBLISH_TIMEOUT; !INTENSET; !INTENCLR; !RUNSTATUS; !REQSTATUS; !CRV; !RREN; !CONFIG; !RR_0; !RR_1; !RR_2; !RR_3; !RR_4; !RR_5; !RR_6; !RR_7; } /// Event generator unit 0 pub mod EGU0_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 1 pub mod EGU0_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 2 pub mod EGU1_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 3 pub mod EGU1_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 4 pub mod EGU2_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 5 pub mod EGU2_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 6 pub mod EGU3_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 7 pub mod EGU3_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 8 pub mod EGU4_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 9 pub mod EGU4_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Event generator unit 10 pub mod EGU5_NS { TASKS_TRIGGER_0; TASKS_TRIGGER_1; TASKS_TRIGGER_2; TASKS_TRIGGER_3; TASKS_TRIGGER_4; TASKS_TRIGGER_5; TASKS_TRIGGER_6; TASKS_TRIGGER_7; TASKS_TRIGGER_8; TASKS_TRIGGER_9; TASKS_TRIGGER_10; TASKS_TRIGGER_11; TASKS_TRIGGER_12; TASKS_TRIGGER_13; TASKS_TRIGGER_14; TASKS_TRIGGER_15; SUBSCRIBE_TRIGGER_0; SUBSCRIBE_TRIGGER_1; SUBSCRIBE_TRIGGER_2; SUBSCRIBE_TRIGGER_3; SUBSCRIBE_TRIGGER_4; SUBSCRIBE_TRIGGER_5; SUBSCRIBE_TRIGGER_6; SUBSCRIBE_TRIGGER_7; SUBSCRIBE_TRIGGER_8; SUBSCRIBE_TRIGGER_9; SUBSCRIBE_TRIGGER_10; SUBSCRIBE_TRIGGER_11; SUBSCRIBE_TRIGGER_12; SUBSCRIBE_TRIGGER_13; SUBSCRIBE_TRIGGER_14; SUBSCRIBE_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; PUBLISH_TRIGGERED_0; PUBLISH_TRIGGERED_1; PUBLISH_TRIGGERED_2; PUBLISH_TRIGGERED_3; PUBLISH_TRIGGERED_4; PUBLISH_TRIGGERED_5; PUBLISH_TRIGGERED_6; PUBLISH_TRIGGERED_7; PUBLISH_TRIGGERED_8; PUBLISH_TRIGGERED_9; PUBLISH_TRIGGERED_10; PUBLISH_TRIGGERED_11; PUBLISH_TRIGGERED_12; PUBLISH_TRIGGERED_13; PUBLISH_TRIGGERED_14; PUBLISH_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Event generator unit 11 pub mod EGU5_S { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; !SUBSCRIBE_TRIGGER_0; !SUBSCRIBE_TRIGGER_1; !SUBSCRIBE_TRIGGER_2; !SUBSCRIBE_TRIGGER_3; !SUBSCRIBE_TRIGGER_4; !SUBSCRIBE_TRIGGER_5; !SUBSCRIBE_TRIGGER_6; !SUBSCRIBE_TRIGGER_7; !SUBSCRIBE_TRIGGER_8; !SUBSCRIBE_TRIGGER_9; !SUBSCRIBE_TRIGGER_10; !SUBSCRIBE_TRIGGER_11; !SUBSCRIBE_TRIGGER_12; !SUBSCRIBE_TRIGGER_13; !SUBSCRIBE_TRIGGER_14; !SUBSCRIBE_TRIGGER_15; !EVENTS_TRIGGERED_0; !EVENTS_TRIGGERED_1; !EVENTS_TRIGGERED_2; !EVENTS_TRIGGERED_3; !EVENTS_TRIGGERED_4; !EVENTS_TRIGGERED_5; !EVENTS_TRIGGERED_6; !EVENTS_TRIGGERED_7; !EVENTS_TRIGGERED_8; !EVENTS_TRIGGERED_9; !EVENTS_TRIGGERED_10; !EVENTS_TRIGGERED_11; !EVENTS_TRIGGERED_12; !EVENTS_TRIGGERED_13; !EVENTS_TRIGGERED_14; !EVENTS_TRIGGERED_15; !PUBLISH_TRIGGERED_0; !PUBLISH_TRIGGERED_1; !PUBLISH_TRIGGERED_2; !PUBLISH_TRIGGERED_3; !PUBLISH_TRIGGERED_4; !PUBLISH_TRIGGERED_5; !PUBLISH_TRIGGERED_6; !PUBLISH_TRIGGERED_7; !PUBLISH_TRIGGERED_8; !PUBLISH_TRIGGERED_9; !PUBLISH_TRIGGERED_10; !PUBLISH_TRIGGERED_11; !PUBLISH_TRIGGERED_12; !PUBLISH_TRIGGERED_13; !PUBLISH_TRIGGERED_14; !PUBLISH_TRIGGERED_15; !INTEN; !INTENSET; !INTENCLR; } /// Pulse width modulation unit 0 pub mod PWM0_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 1 pub mod PWM0_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse width modulation unit 2 pub mod PWM1_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 3 pub mod PWM1_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse width modulation unit 4 pub mod PWM2_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 5 pub mod PWM2_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse width modulation unit 6 pub mod PWM3_NS { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; SUBSCRIBE_STOP; SUBSCRIBE_SEQSTART_0; SUBSCRIBE_SEQSTART_1; SUBSCRIBE_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; PUBLISH_STOPPED; PUBLISH_SEQSTARTED_0; PUBLISH_SEQSTARTED_1; PUBLISH_SEQEND_0; PUBLISH_SEQEND_1; PUBLISH_PWMPERIODEND; PUBLISH_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse width modulation unit 7 pub mod PWM3_S { !TASKS_STOP; !TASKS_SEQSTART_0; !TASKS_SEQSTART_1; !TASKS_NEXTSTEP; !SUBSCRIBE_STOP; !SUBSCRIBE_SEQSTART_0; !SUBSCRIBE_SEQSTART_1; !SUBSCRIBE_NEXTSTEP; !EVENTS_STOPPED; !EVENTS_SEQSTARTED_0; !EVENTS_SEQSTARTED_1; !EVENTS_SEQEND_0; !EVENTS_SEQEND_1; !EVENTS_PWMPERIODEND; !EVENTS_LOOPSDONE; !PUBLISH_STOPPED; !PUBLISH_SEQSTARTED_0; !PUBLISH_SEQSTARTED_1; !PUBLISH_SEQEND_0; !PUBLISH_SEQEND_1; !PUBLISH_PWMPERIODEND; !PUBLISH_LOOPSDONE; !SHORTS; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !MODE; !COUNTERTOP; !PRESCALER; !DECODER; !LOOP; !PSEL_OUT_0; !PSEL_OUT_1; !PSEL_OUT_2; !PSEL_OUT_3; !SEQ_0_PTR; !SEQ_1_PTR; !SEQ_0_CNT; !SEQ_1_CNT; !SEQ_0_REFRESH; !SEQ_1_REFRESH; !SEQ_0_ENDDELAY; !SEQ_1_ENDDELAY; } /// Pulse Density Modulation (Digital Microphone) Interface 0 pub mod PDM_NS { TASKS_START; TASKS_STOP; SUBSCRIBE_START; SUBSCRIBE_STOP; EVENTS_STARTED; EVENTS_STOPPED; EVENTS_END; PUBLISH_STARTED; PUBLISH_STOPPED; PUBLISH_END; INTEN; INTENSET; INTENCLR; ENABLE; PDMCLKCTRL; MODE; GAINL; GAINR; RATIO; SAMPLE_PTR; SAMPLE_MAXCNT; PSEL_CLK; PSEL_DIN; } /// Pulse Density Modulation (Digital Microphone) Interface 1 pub mod PDM_S { !TASKS_START; !TASKS_STOP; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !EVENTS_STARTED; !EVENTS_STOPPED; !EVENTS_END; !PUBLISH_STARTED; !PUBLISH_STOPPED; !PUBLISH_END; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !PDMCLKCTRL; !MODE; !GAINL; !GAINR; !RATIO; !SAMPLE_PTR; !SAMPLE_MAXCNT; !PSEL_CLK; !PSEL_DIN; } /// Inter-IC Sound 0 pub mod I2S_NS { TASKS_START; TASKS_STOP; SUBSCRIBE_START; SUBSCRIBE_STOP; EVENTS_RXPTRUPD; EVENTS_STOPPED; EVENTS_TXPTRUPD; PUBLISH_RXPTRUPD; PUBLISH_STOPPED; PUBLISH_TXPTRUPD; INTEN; INTENSET; INTENCLR; ENABLE; PSEL_MCK; PSEL_SCK; PSEL_LRCK; PSEL_SDIN; PSEL_SDOUT; RXTXD_MAXCNT; TXD_PTR; RXD_PTR; CONFIG_MODE; CONFIG_RXEN; CONFIG_TXEN; CONFIG_MCKEN; CONFIG_MCKFREQ; CONFIG_RATIO; CONFIG_SWIDTH; CONFIG_ALIGN; CONFIG_FORMAT; CONFIG_CHANNELS; } /// Inter-IC Sound 1 pub mod I2S_S { !TASKS_START; !TASKS_STOP; !SUBSCRIBE_START; !SUBSCRIBE_STOP; !EVENTS_RXPTRUPD; !EVENTS_STOPPED; !EVENTS_TXPTRUPD; !PUBLISH_RXPTRUPD; !PUBLISH_STOPPED; !PUBLISH_TXPTRUPD; !INTEN; !INTENSET; !INTENCLR; !ENABLE; !PSEL_MCK; !PSEL_SCK; !PSEL_LRCK; !PSEL_SDIN; !PSEL_SDOUT; !RXTXD_MAXCNT; !TXD_PTR; !RXD_PTR; !CONFIG_MODE; !CONFIG_RXEN; !CONFIG_TXEN; !CONFIG_MCKEN; !CONFIG_MCKFREQ; !CONFIG_RATIO; !CONFIG_SWIDTH; !CONFIG_ALIGN; !CONFIG_FORMAT; !CONFIG_CHANNELS; } /// Inter Processor Communication 0 pub mod IPC_NS { TASKS_SEND_0; TASKS_SEND_1; TASKS_SEND_2; TASKS_SEND_3; TASKS_SEND_4; TASKS_SEND_5; TASKS_SEND_6; TASKS_SEND_7; SUBSCRIBE_SEND_0; SUBSCRIBE_SEND_1; SUBSCRIBE_SEND_2; SUBSCRIBE_SEND_3; SUBSCRIBE_SEND_4; SUBSCRIBE_SEND_5; SUBSCRIBE_SEND_6; SUBSCRIBE_SEND_7; EVENTS_RECEIVE_0; EVENTS_RECEIVE_1; EVENTS_RECEIVE_2; EVENTS_RECEIVE_3; EVENTS_RECEIVE_4; EVENTS_RECEIVE_5; EVENTS_RECEIVE_6; EVENTS_RECEIVE_7; PUBLISH_RECEIVE_0; PUBLISH_RECEIVE_1; PUBLISH_RECEIVE_2; PUBLISH_RECEIVE_3; PUBLISH_RECEIVE_4; PUBLISH_RECEIVE_5; PUBLISH_RECEIVE_6; PUBLISH_RECEIVE_7; INTEN; INTENSET; INTENCLR; INTPEND; SEND_CNF_0; SEND_CNF_1; SEND_CNF_2; SEND_CNF_3; SEND_CNF_4; SEND_CNF_5; SEND_CNF_6; SEND_CNF_7; RECEIVE_CNF_0; RECEIVE_CNF_1; RECEIVE_CNF_2; RECEIVE_CNF_3; RECEIVE_CNF_4; RECEIVE_CNF_5; RECEIVE_CNF_6; RECEIVE_CNF_7; GPMEM_0; GPMEM_1; GPMEM_2; GPMEM_3; } /// Inter Processor Communication 1 pub mod IPC_S { !TASKS_SEND_0; !TASKS_SEND_1; !TASKS_SEND_2; !TASKS_SEND_3; !TASKS_SEND_4; !TASKS_SEND_5; !TASKS_SEND_6; !TASKS_SEND_7; !SUBSCRIBE_SEND_0; !SUBSCRIBE_SEND_1; !SUBSCRIBE_SEND_2; !SUBSCRIBE_SEND_3; !SUBSCRIBE_SEND_4; !SUBSCRIBE_SEND_5; !SUBSCRIBE_SEND_6; !SUBSCRIBE_SEND_7; !EVENTS_RECEIVE_0; !EVENTS_RECEIVE_1; !EVENTS_RECEIVE_2; !EVENTS_RECEIVE_3; !EVENTS_RECEIVE_4; !EVENTS_RECEIVE_5; !EVENTS_RECEIVE_6; !EVENTS_RECEIVE_7; !PUBLISH_RECEIVE_0; !PUBLISH_RECEIVE_1; !PUBLISH_RECEIVE_2; !PUBLISH_RECEIVE_3; !PUBLISH_RECEIVE_4; !PUBLISH_RECEIVE_5; !PUBLISH_RECEIVE_6; !PUBLISH_RECEIVE_7; !INTEN; !INTENSET; !INTENCLR; !INTPEND; !SEND_CNF_0; !SEND_CNF_1; !SEND_CNF_2; !SEND_CNF_3; !SEND_CNF_4; !SEND_CNF_5; !SEND_CNF_6; !SEND_CNF_7; !RECEIVE_CNF_0; !RECEIVE_CNF_1; !RECEIVE_CNF_2; !RECEIVE_CNF_3; !RECEIVE_CNF_4; !RECEIVE_CNF_5; !RECEIVE_CNF_6; !RECEIVE_CNF_7; !GPMEM_0; !GPMEM_1; !GPMEM_2; !GPMEM_3; } /// GPIO Tasks and Events 1 pub mod GPIOTE1_NS { TASKS_OUT_0; TASKS_OUT_1; TASKS_OUT_2; TASKS_OUT_3; TASKS_OUT_4; TASKS_OUT_5; TASKS_OUT_6; TASKS_OUT_7; TASKS_SET_0; TASKS_SET_1; TASKS_SET_2; TASKS_SET_3; TASKS_SET_4; TASKS_SET_5; TASKS_SET_6; TASKS_SET_7; TASKS_CLR_0; TASKS_CLR_1; TASKS_CLR_2; TASKS_CLR_3; TASKS_CLR_4; TASKS_CLR_5; TASKS_CLR_6; TASKS_CLR_7; SUBSCRIBE_OUT_0; SUBSCRIBE_OUT_1; SUBSCRIBE_OUT_2; SUBSCRIBE_OUT_3; SUBSCRIBE_OUT_4; SUBSCRIBE_OUT_5; SUBSCRIBE_OUT_6; SUBSCRIBE_OUT_7; SUBSCRIBE_SET_0; SUBSCRIBE_SET_1; SUBSCRIBE_SET_2; SUBSCRIBE_SET_3; SUBSCRIBE_SET_4; SUBSCRIBE_SET_5; SUBSCRIBE_SET_6; SUBSCRIBE_SET_7; SUBSCRIBE_CLR_0; SUBSCRIBE_CLR_1; SUBSCRIBE_CLR_2; SUBSCRIBE_CLR_3; SUBSCRIBE_CLR_4; SUBSCRIBE_CLR_5; SUBSCRIBE_CLR_6; SUBSCRIBE_CLR_7; EVENTS_IN_0; EVENTS_IN_1; EVENTS_IN_2; EVENTS_IN_3; EVENTS_IN_4; EVENTS_IN_5; EVENTS_IN_6; EVENTS_IN_7; EVENTS_PORT; PUBLISH_IN_0; PUBLISH_IN_1; PUBLISH_IN_2; PUBLISH_IN_3; PUBLISH_IN_4; PUBLISH_IN_5; PUBLISH_IN_6; PUBLISH_IN_7; PUBLISH_PORT; INTENSET; INTENCLR; CONFIG_0; CONFIG_1; CONFIG_2; CONFIG_3; CONFIG_4; CONFIG_5; CONFIG_6; CONFIG_7; } /// Key management unit 0 pub mod KMU_NS { TASKS_PUSH_KEYSLOT; EVENTS_KEYSLOT_PUSHED; EVENTS_KEYSLOT_REVOKED; EVENTS_KEYSLOT_ERROR; INTEN; INTENSET; INTENCLR; INTPEND; STATUS; SELECTKEYSLOT; } /// Key management unit 1 pub mod KMU_S { !TASKS_PUSH_KEYSLOT; !EVENTS_KEYSLOT_PUSHED; !EVENTS_KEYSLOT_REVOKED; !EVENTS_KEYSLOT_ERROR; !INTEN; !INTENSET; !INTENCLR; !INTPEND; !STATUS; !SELECTKEYSLOT; } /// Non-volatile memory controller 0 pub mod NVMC_NS { READY; READYNEXT; CONFIG; ERASEALL; ERASEPAGEPARTIALCFG; ICACHECNF; IHIT; IMISS; CONFIGNS; WRITEUICRNS; } /// Non-volatile memory controller 1 pub mod NVMC_S { !READY; !READYNEXT; !CONFIG; !ERASEALL; !ERASEPAGEPARTIALCFG; !ICACHECNF; !IHIT; !IMISS; !CONFIGNS; !WRITEUICRNS; } /// Volatile Memory controller 0 pub mod VMC_NS { RAM_0_POWER; RAM_1_POWER; RAM_2_POWER; RAM_3_POWER; RAM_4_POWER; RAM_5_POWER; RAM_6_POWER; RAM_7_POWER; RAM_0_POWERSET; RAM_1_POWERSET; RAM_2_POWERSET; RAM_3_POWERSET; RAM_4_POWERSET; RAM_5_POWERSET; RAM_6_POWERSET; RAM_7_POWERSET; RAM_0_POWERCLR; RAM_1_POWERCLR; RAM_2_POWERCLR; RAM_3_POWERCLR; RAM_4_POWERCLR; RAM_5_POWERCLR; RAM_6_POWERCLR; RAM_7_POWERCLR; } /// Volatile Memory controller 1 pub mod VMC_S { !RAM_0_POWER; !RAM_1_POWER; !RAM_2_POWER; !RAM_3_POWER; !RAM_4_POWER; !RAM_5_POWER; !RAM_6_POWER; !RAM_7_POWER; !RAM_0_POWERSET; !RAM_1_POWERSET; !RAM_2_POWERSET; !RAM_3_POWERSET; !RAM_4_POWERSET; !RAM_5_POWERSET; !RAM_6_POWERSET; !RAM_7_POWERSET; !RAM_0_POWERCLR; !RAM_1_POWERCLR; !RAM_2_POWERCLR; !RAM_3_POWERCLR; !RAM_4_POWERCLR; !RAM_5_POWERCLR; !RAM_6_POWERCLR; !RAM_7_POWERCLR; } /// CRYPTOCELL HOST_RGF interface pub mod CC_HOST_RGF_S { HOST_CRYPTOKEY_SEL; HOST_IOT_KPRTL_LOCK; HOST_IOT_KDR0; HOST_IOT_KDR1; HOST_IOT_KDR2; HOST_IOT_KDR3; HOST_IOT_LCS; } /// ARM TrustZone CryptoCell register interface pub mod CRYPTOCELL_S { ENABLE; } /// GPIO Port 0 pub mod P0_NS { OUT; OUTSET; OUTCLR; IN; DIR; DIRSET; DIRCLR; LATCH; DETECTMODE; DETECTMODE_SEC; PIN_CNF_0; PIN_CNF_1; PIN_CNF_2; PIN_CNF_3; PIN_CNF_4; PIN_CNF_5; PIN_CNF_6; PIN_CNF_7; PIN_CNF_8; PIN_CNF_9; PIN_CNF_10; PIN_CNF_11; PIN_CNF_12; PIN_CNF_13; PIN_CNF_14; PIN_CNF_15; PIN_CNF_16; PIN_CNF_17; PIN_CNF_18; PIN_CNF_19; PIN_CNF_20; PIN_CNF_21; PIN_CNF_22; PIN_CNF_23; PIN_CNF_24; PIN_CNF_25; PIN_CNF_26; PIN_CNF_27; PIN_CNF_28; PIN_CNF_29; PIN_CNF_30; PIN_CNF_31; } /// GPIO Port 1 pub mod P0_S { !OUT; !OUTSET; !OUTCLR; !IN; !DIR; !DIRSET; !DIRCLR; !LATCH; !DETECTMODE; !DETECTMODE_SEC; !PIN_CNF_0; !PIN_CNF_1; !PIN_CNF_2; !PIN_CNF_3; !PIN_CNF_4; !PIN_CNF_5; !PIN_CNF_6; !PIN_CNF_7; !PIN_CNF_8; !PIN_CNF_9; !PIN_CNF_10; !PIN_CNF_11; !PIN_CNF_12; !PIN_CNF_13; !PIN_CNF_14; !PIN_CNF_15; !PIN_CNF_16; !PIN_CNF_17; !PIN_CNF_18; !PIN_CNF_19; !PIN_CNF_20; !PIN_CNF_21; !PIN_CNF_22; !PIN_CNF_23; !PIN_CNF_24; !PIN_CNF_25; !PIN_CNF_26; !PIN_CNF_27; !PIN_CNF_28; !PIN_CNF_29; !PIN_CNF_30; !PIN_CNF_31; } } => { ... }; }
Defines an index of nrf9160 register tokens.