Macro drone_nrf_map_pieces::nrf_reg_tokens [−][src]
macro_rules! nrf_reg_tokens { reg::tokens! { /// Defines an index of nrf52 register tokens. pub macro nrf_reg_tokens; use macro drone_cortexm::map::cortexm_reg_tokens; super::inner; crate::reg; /// Factory Information Configuration Registers pub mod FICR { CODEPAGESIZE; CODESIZE; DEVICEID_0; DEVICEID_1; ER_0; ER_1; ER_2; ER_3; IR_0; IR_1; IR_2; IR_3; DEVICEADDRTYPE; DEVICEADDR_0; DEVICEADDR_1; NFC_TAGHEADER0; NFC_TAGHEADER1; NFC_TAGHEADER2; NFC_TAGHEADER3; TEMP_A0; TEMP_A1; TEMP_A2; TEMP_A3; TEMP_A4; TEMP_A5; TEMP_B0; TEMP_B1; TEMP_B2; TEMP_B3; TEMP_B4; TEMP_B5; TEMP_T0; TEMP_T1; TEMP_T2; TEMP_T3; TEMP_T4; INFO_PART; INFO_VARIANT; INFO_PACKAGE; INFO_RAM; INFO_FLASH; INFO_UNUSED0_0; INFO_UNUSED0_1; INFO_UNUSED0_2; } /// User Information Configuration Registers pub mod UICR { UNUSED0; UNUSED1; UNUSED2; UNUSED3; NRFFW_0; NRFFW_1; NRFFW_2; NRFFW_3; NRFFW_4; NRFFW_5; NRFFW_6; NRFFW_7; NRFFW_8; NRFFW_9; NRFFW_10; NRFFW_11; NRFFW_12; NRFFW_13; NRFFW_14; NRFHW_0; NRFHW_1; NRFHW_2; NRFHW_3; NRFHW_4; NRFHW_5; NRFHW_6; NRFHW_7; NRFHW_8; NRFHW_9; NRFHW_10; NRFHW_11; CUSTOMER_0; CUSTOMER_1; CUSTOMER_2; CUSTOMER_3; CUSTOMER_4; CUSTOMER_5; CUSTOMER_6; CUSTOMER_7; CUSTOMER_8; CUSTOMER_9; CUSTOMER_10; CUSTOMER_11; CUSTOMER_12; CUSTOMER_13; CUSTOMER_14; CUSTOMER_15; CUSTOMER_16; CUSTOMER_17; CUSTOMER_18; CUSTOMER_19; CUSTOMER_20; CUSTOMER_21; CUSTOMER_22; CUSTOMER_23; CUSTOMER_24; CUSTOMER_25; CUSTOMER_26; CUSTOMER_27; CUSTOMER_28; CUSTOMER_29; CUSTOMER_30; CUSTOMER_31; PSELRESET_0; PSELRESET_1; APPROTECT; NFCPINS; } /// Block Protect pub mod BPROT { CONFIG0; CONFIG1; DISABLEINDEBUG; UNUSED0; CONFIG2; CONFIG3; } /// Power control pub mod POWER { TASKS_CONSTLAT; TASKS_LOWPWR; EVENTS_POFWARN; EVENTS_SLEEPENTER; EVENTS_SLEEPEXIT; INTENSET; INTENCLR; RESETREAS; RAMSTATUS; SYSTEMOFF; POFCON; GPREGRET; GPREGRET2; RAMON; RAMONB; DCDCEN; RAM_0_POWER; RAM_1_POWER; RAM_2_POWER; RAM_3_POWER; RAM_4_POWER; RAM_5_POWER; RAM_6_POWER; RAM_7_POWER; RAM_0_POWERSET; RAM_1_POWERSET; RAM_2_POWERSET; RAM_3_POWERSET; RAM_4_POWERSET; RAM_5_POWERSET; RAM_6_POWERSET; RAM_7_POWERSET; RAM_0_POWERCLR; RAM_1_POWERCLR; RAM_2_POWERCLR; RAM_3_POWERCLR; RAM_4_POWERCLR; RAM_5_POWERCLR; RAM_6_POWERCLR; RAM_7_POWERCLR; } /// Clock control pub mod CLOCK { !INTENSET; !INTENCLR; TASKS_HFCLKSTART; TASKS_HFCLKSTOP; TASKS_LFCLKSTART; TASKS_LFCLKSTOP; TASKS_CAL; TASKS_CTSTART; TASKS_CTSTOP; EVENTS_HFCLKSTARTED; EVENTS_LFCLKSTARTED; EVENTS_DONE; EVENTS_CTTO; HFCLKRUN; HFCLKSTAT; LFCLKRUN; LFCLKSTAT; LFCLKSRCCOPY; LFCLKSRC; CTIV; TRACECONFIG; } /// 2.4 GHz Radio pub mod RADIO { TASKS_TXEN; TASKS_RXEN; TASKS_START; TASKS_STOP; TASKS_DISABLE; TASKS_RSSISTART; TASKS_RSSISTOP; TASKS_BCSTART; TASKS_BCSTOP; EVENTS_READY; EVENTS_ADDRESS; EVENTS_PAYLOAD; EVENTS_END; EVENTS_DISABLED; EVENTS_DEVMATCH; EVENTS_DEVMISS; EVENTS_RSSIEND; EVENTS_BCMATCH; EVENTS_CRCOK; EVENTS_CRCERROR; SHORTS; INTENSET; INTENCLR; CRCSTATUS; RXMATCH; RXCRC; DAI; PACKETPTR; FREQUENCY; TXPOWER; MODE; PCNF0; PCNF1; BASE0; BASE1; PREFIX0; PREFIX1; TXADDRESS; RXADDRESSES; CRCCNF; CRCPOLY; CRCINIT; UNUSED0; TIFS; RSSISAMPLE; STATE; DATAWHITEIV; BCC; DAB_0; DAB_1; DAB_2; DAB_3; DAB_4; DAB_5; DAB_6; DAB_7; DAP_0; DAP_1; DAP_2; DAP_3; DAP_4; DAP_5; DAP_6; DAP_7; DACNF; MODECNF0; POWER; } /// UART with EasyDMA pub mod UARTE0 { TASKS_STARTRX; TASKS_STOPRX; TASKS_STARTTX; TASKS_STOPTX; TASKS_FLUSHRX; EVENTS_CTS; EVENTS_NCTS; EVENTS_RXDRDY; EVENTS_ENDRX; EVENTS_TXDRDY; EVENTS_ENDTX; EVENTS_ERROR; EVENTS_RXTO; EVENTS_RXSTARTED; EVENTS_TXSTARTED; EVENTS_TXSTOPPED; SHORTS; INTEN; INTENSET; INTENCLR; ERRORSRC; ENABLE; BAUDRATE; CONFIG; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; PSEL_RTS; PSEL_TXD; PSEL_CTS; PSEL_RXD; } /// Universal Asynchronous Receiver/Transmitter pub mod UART0 { !TASKS_STARTRX; !TASKS_STOPRX; !TASKS_STARTTX; !TASKS_STOPTX; !EVENTS_CTS; !EVENTS_NCTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_ERROR; !EVENTS_RXTO; !SHORTS; !INTENSET; !INTENCLR; !ERRORSRC; !ENABLE; !BAUDRATE; !CONFIG; !PSELRTS; !PSELTXD; !PSELCTS; !PSELRXD; TASKS_SUSPEND; RXD; TXD; } /// Serial Peripheral Interface Master with EasyDMA 0 pub mod SPIM0 { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 0 pub mod TWIM0 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 pub mod TWIS0 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; EVENTS_WRITE; EVENTS_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Interface 0 pub mod TWI0 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !PSELSCL; !PSELSDA; !TASKS_STARTRX; !TASKS_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !ERRORSRC; !ADDRESS; !EVENTS_RXDREADY; !RXD; !TXD; EVENTS_TXDSENT; EVENTS_BB; } /// SPI Slave 0 pub mod SPIS0 { !EVENTS_END; !EVENTS_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; EVENTS_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// Serial Peripheral Interface 0 pub mod SPI0 { !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; EVENTS_READY; RXD; TXD; } /// Serial Peripheral Interface Master with EasyDMA 1 pub mod SPIM1 { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 1 pub mod TWIM1 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 pub mod TWIS1 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; EVENTS_WRITE; EVENTS_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Interface 1 pub mod TWI1 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !PSELSCL; !PSELSDA; !TASKS_STARTRX; !TASKS_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !ERRORSRC; !ADDRESS; !EVENTS_RXDREADY; !RXD; !TXD; EVENTS_TXDSENT; EVENTS_BB; } /// SPI Slave 1 pub mod SPIS1 { !EVENTS_END; !EVENTS_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; EVENTS_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// Serial Peripheral Interface 1 pub mod SPI1 { !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; EVENTS_READY; RXD; TXD; } /// NFC-A compatible radio pub mod NFCT { TASKS_ACTIVATE; TASKS_DISABLE; TASKS_SENSE; TASKS_STARTTX; TASKS_ENABLERXDATA; TASKS_GOIDLE; TASKS_GOSLEEP; EVENTS_READY; EVENTS_FIELDDETECTED; EVENTS_FIELDLOST; EVENTS_TXFRAMESTART; EVENTS_TXFRAMEEND; EVENTS_RXFRAMESTART; EVENTS_RXFRAMEEND; EVENTS_ERROR; EVENTS_RXERROR; EVENTS_ENDRX; EVENTS_ENDTX; EVENTS_AUTOCOLRESSTARTED; EVENTS_COLLISION; EVENTS_SELECTED; EVENTS_STARTED; SHORTS; INTEN; INTENSET; INTENCLR; ERRORSTATUS; CURRENTLOADCTRL; FIELDPRESENT; FRAMEDELAYMIN; FRAMEDELAYMAX; FRAMEDELAYMODE; PACKETPTR; MAXLEN; NFCID1_LAST; NFCID1_2ND_LAST; NFCID1_3RD_LAST; SENSRES; SELRES; RXD_FRAMECONFIG; RXD_AMOUNT; TXD_FRAMECONFIG; TXD_AMOUNT; FRAMESTATUS_RX; } /// GPIO Tasks and Events pub mod GPIOTE { TASKS_OUT_0; TASKS_OUT_1; TASKS_OUT_2; TASKS_OUT_3; TASKS_OUT_4; TASKS_OUT_5; TASKS_OUT_6; TASKS_OUT_7; TASKS_SET_0; TASKS_SET_1; TASKS_SET_2; TASKS_SET_3; TASKS_SET_4; TASKS_SET_5; TASKS_SET_6; TASKS_SET_7; TASKS_CLR_0; TASKS_CLR_1; TASKS_CLR_2; TASKS_CLR_3; TASKS_CLR_4; TASKS_CLR_5; TASKS_CLR_6; TASKS_CLR_7; EVENTS_IN_0; EVENTS_IN_1; EVENTS_IN_2; EVENTS_IN_3; EVENTS_IN_4; EVENTS_IN_5; EVENTS_IN_6; EVENTS_IN_7; EVENTS_PORT; INTENSET; INTENCLR; CONFIG_0; CONFIG_1; CONFIG_2; CONFIG_3; CONFIG_4; CONFIG_5; CONFIG_6; CONFIG_7; } /// Analog to Digital Converter pub mod SAADC { TASKS_START; TASKS_SAMPLE; TASKS_STOP; TASKS_CALIBRATEOFFSET; EVENTS_STARTED; EVENTS_END; EVENTS_DONE; EVENTS_RESULTDONE; EVENTS_CALIBRATEDONE; EVENTS_STOPPED; INTEN; INTENSET; INTENCLR; STATUS; ENABLE; RESOLUTION; OVERSAMPLE; SAMPLERATE; RESULT_PTR; RESULT_MAXCNT; RESULT_AMOUNT; CH_0_PSELP; CH_1_PSELP; CH_2_PSELP; CH_3_PSELP; CH_4_PSELP; CH_5_PSELP; CH_6_PSELP; CH_7_PSELP; CH_0_PSELN; CH_1_PSELN; CH_2_PSELN; CH_3_PSELN; CH_4_PSELN; CH_5_PSELN; CH_6_PSELN; CH_7_PSELN; CH_0_CONFIG; CH_1_CONFIG; CH_2_CONFIG; CH_3_CONFIG; CH_4_CONFIG; CH_5_CONFIG; CH_6_CONFIG; CH_7_CONFIG; CH_0_LIMIT; CH_1_LIMIT; CH_2_LIMIT; CH_3_LIMIT; CH_4_LIMIT; CH_5_LIMIT; CH_6_LIMIT; CH_7_LIMIT; EVENTS_CH_0_LIMITH; EVENTS_CH_1_LIMITH; EVENTS_CH_2_LIMITH; EVENTS_CH_3_LIMITH; EVENTS_CH_4_LIMITH; EVENTS_CH_5_LIMITH; EVENTS_CH_6_LIMITH; EVENTS_CH_7_LIMITH; EVENTS_CH_0_LIMITL; EVENTS_CH_1_LIMITL; EVENTS_CH_2_LIMITL; EVENTS_CH_3_LIMITL; EVENTS_CH_4_LIMITL; EVENTS_CH_5_LIMITL; EVENTS_CH_6_LIMITL; EVENTS_CH_7_LIMITL; } /// Timer/Counter 0 pub mod TIMER0 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 1 pub mod TIMER1 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 2 pub mod TIMER2 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Real time counter 0 pub mod RTC0 { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Temperature Sensor pub mod TEMP { TASKS_START; TASKS_STOP; EVENTS_DATARDY; INTENSET; INTENCLR; TEMP; A0; A1; A2; A3; A4; A5; B0; B1; B2; B3; B4; B5; T0; T1; T2; T3; T4; } /// Random Number Generator pub mod RNG { TASKS_START; TASKS_STOP; EVENTS_VALRDY; SHORTS; INTENSET; INTENCLR; CONFIG; VALUE; } /// AES ECB Mode Encryption pub mod ECB { TASKS_STARTECB; TASKS_STOPECB; EVENTS_ENDECB; EVENTS_ERRORECB; INTENSET; INTENCLR; ECBDATAPTR; } /// AES CCM Mode Encryption pub mod CCM { TASKS_KSGEN; TASKS_CRYPT; TASKS_STOP; EVENTS_ENDKSGEN; EVENTS_ENDCRYPT; EVENTS_ERROR; SHORTS; INTENSET; INTENCLR; MICSTATUS; ENABLE; MODE; CNFPTR; INPTR; OUTPTR; SCRATCHPTR; } /// Accelerated Address Resolver pub mod AAR { !TASKS_START; !TASKS_STOP; !EVENTS_END; !EVENTS_RESOLVED; !EVENTS_NOTRESOLVED; !INTENSET; !INTENCLR; !STATUS; !ENABLE; !NIRK; !IRKPTR; !ADDRPTR; !SCRATCHPTR; } /// Watchdog Timer pub mod WDT { TASKS_START; EVENTS_TIMEOUT; INTENSET; INTENCLR; RUNSTATUS; REQSTATUS; CRV; RREN; CONFIG; RR_0; RR_1; RR_2; RR_3; RR_4; RR_5; RR_6; RR_7; } /// Real time counter 1 pub mod RTC1 { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Quadrature Decoder pub mod QDEC { TASKS_START; TASKS_STOP; TASKS_READCLRACC; TASKS_RDCLRACC; TASKS_RDCLRDBL; EVENTS_SAMPLERDY; EVENTS_REPORTRDY; EVENTS_ACCOF; EVENTS_DBLRDY; EVENTS_STOPPED; SHORTS; INTENSET; INTENCLR; ENABLE; LEDPOL; SAMPLEPER; SAMPLE; REPORTPER; ACC; ACCREAD; DBFEN; LEDPRE; ACCDBL; ACCDBLREAD; PSEL_LED; PSEL_A; PSEL_B; } /// Comparator pub mod COMP { TASKS_START; TASKS_STOP; TASKS_SAMPLE; EVENTS_READY; EVENTS_DOWN; EVENTS_UP; EVENTS_CROSS; SHORTS; INTEN; INTENSET; INTENCLR; RESULT; ENABLE; PSEL; REFSEL; EXTREFSEL; TH; MODE; HYST; ISOURCE; } /// Low Power Comparator pub mod LPCOMP { !TASKS_START; !TASKS_STOP; !TASKS_SAMPLE; !EVENTS_READY; !EVENTS_DOWN; !EVENTS_UP; !EVENTS_CROSS; !SHORTS; !INTENSET; !INTENCLR; !RESULT; !ENABLE; !PSEL; !REFSEL; !EXTREFSEL; !HYST; ANADETECT; } /// Software interrupt 0 pub mod SWI0 { UNUSED; } /// Event Generator Unit 0 pub mod EGU0 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 1 pub mod SWI1 { UNUSED; } /// Event Generator Unit 1 pub mod EGU1 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 2 pub mod SWI2 { UNUSED; } /// Event Generator Unit 2 pub mod EGU2 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 3 pub mod SWI3 { UNUSED; } /// Event Generator Unit 3 pub mod EGU3 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 4 pub mod SWI4 { UNUSED; } /// Event Generator Unit 4 pub mod EGU4 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 5 pub mod SWI5 { UNUSED; } /// Event Generator Unit 5 pub mod EGU5 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Timer/Counter 3 pub mod TIMER3 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 4 pub mod TIMER4 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Pulse Width Modulation Unit 0 pub mod PWM0 { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse Density Modulation (Digital Microphone) Interface pub mod PDM { TASKS_START; TASKS_STOP; EVENTS_STARTED; EVENTS_STOPPED; EVENTS_END; INTEN; INTENSET; INTENCLR; ENABLE; PDMCLKCTRL; MODE; GAINL; GAINR; SAMPLE_PTR; SAMPLE_MAXCNT; PSEL_CLK; PSEL_DIN; } /// Non Volatile Memory Controller pub mod NVMC { READY; CONFIG; ERASEPAGE; !ERASEPCR1; ERASEALL; ERASEPCR0; ERASEUICR; ICACHECNF; IHIT; IMISS; } /// Programmable Peripheral Interconnect pub mod PPI { CHEN; CHENSET; CHENCLR; CHG_0; CHG_1; CHG_2; CHG_3; CHG_4; CHG_5; FORK_0_TEP; FORK_1_TEP; FORK_2_TEP; FORK_3_TEP; FORK_4_TEP; FORK_5_TEP; FORK_6_TEP; FORK_7_TEP; FORK_8_TEP; FORK_9_TEP; FORK_10_TEP; FORK_11_TEP; FORK_12_TEP; FORK_13_TEP; FORK_14_TEP; FORK_15_TEP; FORK_16_TEP; FORK_17_TEP; FORK_18_TEP; FORK_19_TEP; FORK_20_TEP; FORK_21_TEP; FORK_22_TEP; FORK_23_TEP; FORK_24_TEP; FORK_25_TEP; FORK_26_TEP; FORK_27_TEP; FORK_28_TEP; FORK_29_TEP; FORK_30_TEP; FORK_31_TEP; CH_0_EEP; CH_1_EEP; CH_2_EEP; CH_3_EEP; CH_4_EEP; CH_5_EEP; CH_6_EEP; CH_7_EEP; CH_8_EEP; CH_9_EEP; CH_10_EEP; CH_11_EEP; CH_12_EEP; CH_13_EEP; CH_14_EEP; CH_15_EEP; CH_16_EEP; CH_17_EEP; CH_18_EEP; CH_19_EEP; CH_0_TEP; CH_1_TEP; CH_2_TEP; CH_3_TEP; CH_4_TEP; CH_5_TEP; CH_6_TEP; CH_7_TEP; CH_8_TEP; CH_9_TEP; CH_10_TEP; CH_11_TEP; CH_12_TEP; CH_13_TEP; CH_14_TEP; CH_15_TEP; CH_16_TEP; CH_17_TEP; CH_18_TEP; CH_19_TEP; TASKS_CHG_0_EN; TASKS_CHG_1_EN; TASKS_CHG_2_EN; TASKS_CHG_3_EN; TASKS_CHG_4_EN; TASKS_CHG_5_EN; TASKS_CHG_0_DIS; TASKS_CHG_1_DIS; TASKS_CHG_2_DIS; TASKS_CHG_3_DIS; TASKS_CHG_4_DIS; TASKS_CHG_5_DIS; } /// Memory Watch Unit pub mod MWU { INTEN; INTENSET; INTENCLR; NMIEN; NMIENSET; NMIENCLR; REGIONEN; REGIONENSET; REGIONENCLR; PREGION_0_START; PREGION_1_START; PREGION_0_END; PREGION_1_END; PREGION_0_SUBS; PREGION_1_SUBS; REGION_0_START; REGION_1_START; REGION_2_START; REGION_3_START; REGION_0_END; REGION_1_END; REGION_2_END; REGION_3_END; PERREGION_0_SUBSTATWA; PERREGION_1_SUBSTATWA; PERREGION_0_SUBSTATRA; PERREGION_1_SUBSTATRA; EVENTS_PREGION_0_WA; EVENTS_PREGION_1_WA; EVENTS_PREGION_0_RA; EVENTS_PREGION_1_RA; EVENTS_REGION_0_WA; EVENTS_REGION_1_WA; EVENTS_REGION_2_WA; EVENTS_REGION_3_WA; EVENTS_REGION_0_RA; EVENTS_REGION_1_RA; EVENTS_REGION_2_RA; EVENTS_REGION_3_RA; } /// Pulse Width Modulation Unit 1 pub mod PWM1 { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse Width Modulation Unit 2 pub mod PWM2 { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Serial Peripheral Interface Master with EasyDMA 2 pub mod SPIM2 { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// SPI Slave 2 pub mod SPIS2 { !EVENTS_END; !EVENTS_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; EVENTS_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// Serial Peripheral Interface 2 pub mod SPI2 { !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; EVENTS_READY; RXD; TXD; } /// Real time counter 2 pub mod RTC2 { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Inter-IC Sound pub mod I2S { TASKS_START; TASKS_STOP; EVENTS_RXPTRUPD; EVENTS_STOPPED; EVENTS_TXPTRUPD; INTEN; INTENSET; INTENCLR; ENABLE; PSEL_MCK; PSEL_SCK; PSEL_LRCK; PSEL_SDIN; PSEL_SDOUT; RXTXD_MAXCNT; TXD_PTR; RXD_PTR; CONFIG_MODE; CONFIG_RXEN; CONFIG_TXEN; CONFIG_MCKEN; CONFIG_MCKFREQ; CONFIG_RATIO; CONFIG_SWIDTH; CONFIG_ALIGN; CONFIG_FORMAT; CONFIG_CHANNELS; } /// FPU pub mod FPU { UNUSED; } /// GPIO Port 1 pub mod P0 { OUT; OUTSET; OUTCLR; IN; DIR; DIRSET; DIRCLR; LATCH; DETECTMODE; PIN_CNF_0; PIN_CNF_1; PIN_CNF_2; PIN_CNF_3; PIN_CNF_4; PIN_CNF_5; PIN_CNF_6; PIN_CNF_7; PIN_CNF_8; PIN_CNF_9; PIN_CNF_10; PIN_CNF_11; PIN_CNF_12; PIN_CNF_13; PIN_CNF_14; PIN_CNF_15; PIN_CNF_16; PIN_CNF_17; PIN_CNF_18; PIN_CNF_19; PIN_CNF_20; PIN_CNF_21; PIN_CNF_22; PIN_CNF_23; PIN_CNF_24; PIN_CNF_25; PIN_CNF_26; PIN_CNF_27; PIN_CNF_28; PIN_CNF_29; PIN_CNF_30; PIN_CNF_31; } } => { ... }; reg::tokens! { /// Defines an index of nrf52 register tokens. pub macro nrf_reg_tokens; use macro drone_cortexm::map::cortexm_reg_tokens; super::inner; crate::reg; /// Factory Information Configuration Registers pub mod FICR { CODEPAGESIZE; CODESIZE; DEVICEID_0; DEVICEID_1; ER_0; ER_1; ER_2; ER_3; IR_0; IR_1; IR_2; IR_3; DEVICEADDRTYPE; DEVICEADDR_0; DEVICEADDR_1; NFC_TAGHEADER0; NFC_TAGHEADER1; NFC_TAGHEADER2; NFC_TAGHEADER3; TEMP_A0; TEMP_A1; TEMP_A2; TEMP_A3; TEMP_A4; TEMP_A5; TEMP_B0; TEMP_B1; TEMP_B2; TEMP_B3; TEMP_B4; TEMP_B5; TEMP_T0; TEMP_T1; TEMP_T2; TEMP_T3; TEMP_T4; INFO_PART; INFO_VARIANT; INFO_PACKAGE; INFO_RAM; INFO_FLASH; INFO_UNUSED0_0; INFO_UNUSED0_1; INFO_UNUSED0_2; } /// User Information Configuration Registers pub mod UICR { UNUSED0; UNUSED1; UNUSED2; UNUSED3; NRFFW_0; NRFFW_1; NRFFW_2; NRFFW_3; NRFFW_4; NRFFW_5; NRFFW_6; NRFFW_7; NRFFW_8; NRFFW_9; NRFFW_10; NRFFW_11; NRFFW_12; NRFFW_13; NRFFW_14; NRFHW_0; NRFHW_1; NRFHW_2; NRFHW_3; NRFHW_4; NRFHW_5; NRFHW_6; NRFHW_7; NRFHW_8; NRFHW_9; NRFHW_10; NRFHW_11; CUSTOMER_0; CUSTOMER_1; CUSTOMER_2; CUSTOMER_3; CUSTOMER_4; CUSTOMER_5; CUSTOMER_6; CUSTOMER_7; CUSTOMER_8; CUSTOMER_9; CUSTOMER_10; CUSTOMER_11; CUSTOMER_12; CUSTOMER_13; CUSTOMER_14; CUSTOMER_15; CUSTOMER_16; CUSTOMER_17; CUSTOMER_18; CUSTOMER_19; CUSTOMER_20; CUSTOMER_21; CUSTOMER_22; CUSTOMER_23; CUSTOMER_24; CUSTOMER_25; CUSTOMER_26; CUSTOMER_27; CUSTOMER_28; CUSTOMER_29; CUSTOMER_30; CUSTOMER_31; PSELRESET_0; PSELRESET_1; APPROTECT; NFCPINS; } /// Block Protect pub mod BPROT { CONFIG0; CONFIG1; DISABLEINDEBUG; UNUSED0; CONFIG2; CONFIG3; } /// Power control pub mod POWER { TASKS_CONSTLAT; TASKS_LOWPWR; EVENTS_POFWARN; EVENTS_SLEEPENTER; EVENTS_SLEEPEXIT; INTENSET; INTENCLR; RESETREAS; RAMSTATUS; SYSTEMOFF; POFCON; GPREGRET; GPREGRET2; RAMON; RAMONB; DCDCEN; RAM_0_POWER; RAM_1_POWER; RAM_2_POWER; RAM_3_POWER; RAM_4_POWER; RAM_5_POWER; RAM_6_POWER; RAM_7_POWER; RAM_0_POWERSET; RAM_1_POWERSET; RAM_2_POWERSET; RAM_3_POWERSET; RAM_4_POWERSET; RAM_5_POWERSET; RAM_6_POWERSET; RAM_7_POWERSET; RAM_0_POWERCLR; RAM_1_POWERCLR; RAM_2_POWERCLR; RAM_3_POWERCLR; RAM_4_POWERCLR; RAM_5_POWERCLR; RAM_6_POWERCLR; RAM_7_POWERCLR; } /// Clock control pub mod CLOCK { !INTENSET; !INTENCLR; TASKS_HFCLKSTART; TASKS_HFCLKSTOP; TASKS_LFCLKSTART; TASKS_LFCLKSTOP; TASKS_CAL; TASKS_CTSTART; TASKS_CTSTOP; EVENTS_HFCLKSTARTED; EVENTS_LFCLKSTARTED; EVENTS_DONE; EVENTS_CTTO; HFCLKRUN; HFCLKSTAT; LFCLKRUN; LFCLKSTAT; LFCLKSRCCOPY; LFCLKSRC; CTIV; TRACECONFIG; } /// 2.4 GHz Radio pub mod RADIO { TASKS_TXEN; TASKS_RXEN; TASKS_START; TASKS_STOP; TASKS_DISABLE; TASKS_RSSISTART; TASKS_RSSISTOP; TASKS_BCSTART; TASKS_BCSTOP; EVENTS_READY; EVENTS_ADDRESS; EVENTS_PAYLOAD; EVENTS_END; EVENTS_DISABLED; EVENTS_DEVMATCH; EVENTS_DEVMISS; EVENTS_RSSIEND; EVENTS_BCMATCH; EVENTS_CRCOK; EVENTS_CRCERROR; SHORTS; INTENSET; INTENCLR; CRCSTATUS; RXMATCH; RXCRC; DAI; PACKETPTR; FREQUENCY; TXPOWER; MODE; PCNF0; PCNF1; BASE0; BASE1; PREFIX0; PREFIX1; TXADDRESS; RXADDRESSES; CRCCNF; CRCPOLY; CRCINIT; UNUSED0; TIFS; RSSISAMPLE; STATE; DATAWHITEIV; BCC; DAB_0; DAB_1; DAB_2; DAB_3; DAB_4; DAB_5; DAB_6; DAB_7; DAP_0; DAP_1; DAP_2; DAP_3; DAP_4; DAP_5; DAP_6; DAP_7; DACNF; MODECNF0; POWER; } /// UART with EasyDMA pub mod UARTE0 { TASKS_STARTRX; TASKS_STOPRX; TASKS_STARTTX; TASKS_STOPTX; TASKS_FLUSHRX; EVENTS_CTS; EVENTS_NCTS; EVENTS_RXDRDY; EVENTS_ENDRX; EVENTS_TXDRDY; EVENTS_ENDTX; EVENTS_ERROR; EVENTS_RXTO; EVENTS_RXSTARTED; EVENTS_TXSTARTED; EVENTS_TXSTOPPED; SHORTS; INTEN; INTENSET; INTENCLR; ERRORSRC; ENABLE; BAUDRATE; CONFIG; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; PSEL_RTS; PSEL_TXD; PSEL_CTS; PSEL_RXD; } /// Universal Asynchronous Receiver/Transmitter pub mod UART0 { !TASKS_STARTRX; !TASKS_STOPRX; !TASKS_STARTTX; !TASKS_STOPTX; !EVENTS_CTS; !EVENTS_NCTS; !EVENTS_RXDRDY; !EVENTS_TXDRDY; !EVENTS_ERROR; !EVENTS_RXTO; !SHORTS; !INTENSET; !INTENCLR; !ERRORSRC; !ENABLE; !BAUDRATE; !CONFIG; !PSELRTS; !PSELTXD; !PSELCTS; !PSELRXD; TASKS_SUSPEND; RXD; TXD; } /// Serial Peripheral Interface Master with EasyDMA 0 pub mod SPIM0 { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 0 pub mod TWIM0 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 0 pub mod TWIS0 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; EVENTS_WRITE; EVENTS_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Interface 0 pub mod TWI0 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !PSELSCL; !PSELSDA; !TASKS_STARTRX; !TASKS_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !ERRORSRC; !ADDRESS; !EVENTS_RXDREADY; !RXD; !TXD; EVENTS_TXDSENT; EVENTS_BB; } /// SPI Slave 0 pub mod SPIS0 { !EVENTS_END; !EVENTS_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; EVENTS_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// Serial Peripheral Interface 0 pub mod SPI0 { !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; EVENTS_READY; RXD; TXD; } /// Serial Peripheral Interface Master with EasyDMA 1 pub mod SPIM1 { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// I2C compatible Two-Wire Master Interface with EasyDMA 1 pub mod TWIM1 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !TXD_LIST; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !RXD_LIST; !PSEL_SCL; !PSEL_SDA; TASKS_STARTRX; TASKS_STARTTX; EVENTS_ERROR; EVENTS_SUSPENDED; EVENTS_TXSTARTED; EVENTS_LASTRX; EVENTS_LASTTX; INTEN; ERRORSRC; ADDRESS; } /// I2C compatible Two-Wire Slave Interface with EasyDMA 1 pub mod TWIS1 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !EVENTS_RXSTARTED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCL; !PSEL_SDA; !EVENTS_ERROR; !EVENTS_TXSTARTED; !INTEN; !ADDRESS_0; !ADDRESS_1; TASKS_PREPARERX; TASKS_PREPARETX; EVENTS_WRITE; EVENTS_READ; ERRORSRC; MATCH; CONFIG; } /// I2C compatible Two-Wire Interface 1 pub mod TWI1 { !TASKS_STOP; !TASKS_SUSPEND; !TASKS_RESUME; !EVENTS_STOPPED; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !PSELSCL; !PSELSDA; !TASKS_STARTRX; !TASKS_STARTTX; !EVENTS_ERROR; !EVENTS_SUSPENDED; !ERRORSRC; !ADDRESS; !EVENTS_RXDREADY; !RXD; !TXD; EVENTS_TXDSENT; EVENTS_BB; } /// SPI Slave 1 pub mod SPIS1 { !EVENTS_END; !EVENTS_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; EVENTS_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// Serial Peripheral Interface 1 pub mod SPI1 { !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; EVENTS_READY; RXD; TXD; } /// NFC-A compatible radio pub mod NFCT { TASKS_ACTIVATE; TASKS_DISABLE; TASKS_SENSE; TASKS_STARTTX; TASKS_ENABLERXDATA; TASKS_GOIDLE; TASKS_GOSLEEP; EVENTS_READY; EVENTS_FIELDDETECTED; EVENTS_FIELDLOST; EVENTS_TXFRAMESTART; EVENTS_TXFRAMEEND; EVENTS_RXFRAMESTART; EVENTS_RXFRAMEEND; EVENTS_ERROR; EVENTS_RXERROR; EVENTS_ENDRX; EVENTS_ENDTX; EVENTS_AUTOCOLRESSTARTED; EVENTS_COLLISION; EVENTS_SELECTED; EVENTS_STARTED; SHORTS; INTEN; INTENSET; INTENCLR; ERRORSTATUS; CURRENTLOADCTRL; FIELDPRESENT; FRAMEDELAYMIN; FRAMEDELAYMAX; FRAMEDELAYMODE; PACKETPTR; MAXLEN; NFCID1_LAST; NFCID1_2ND_LAST; NFCID1_3RD_LAST; SENSRES; SELRES; RXD_FRAMECONFIG; RXD_AMOUNT; TXD_FRAMECONFIG; TXD_AMOUNT; FRAMESTATUS_RX; } /// GPIO Tasks and Events pub mod GPIOTE { TASKS_OUT_0; TASKS_OUT_1; TASKS_OUT_2; TASKS_OUT_3; TASKS_OUT_4; TASKS_OUT_5; TASKS_OUT_6; TASKS_OUT_7; TASKS_SET_0; TASKS_SET_1; TASKS_SET_2; TASKS_SET_3; TASKS_SET_4; TASKS_SET_5; TASKS_SET_6; TASKS_SET_7; TASKS_CLR_0; TASKS_CLR_1; TASKS_CLR_2; TASKS_CLR_3; TASKS_CLR_4; TASKS_CLR_5; TASKS_CLR_6; TASKS_CLR_7; EVENTS_IN_0; EVENTS_IN_1; EVENTS_IN_2; EVENTS_IN_3; EVENTS_IN_4; EVENTS_IN_5; EVENTS_IN_6; EVENTS_IN_7; EVENTS_PORT; INTENSET; INTENCLR; CONFIG_0; CONFIG_1; CONFIG_2; CONFIG_3; CONFIG_4; CONFIG_5; CONFIG_6; CONFIG_7; } /// Analog to Digital Converter pub mod SAADC { TASKS_START; TASKS_SAMPLE; TASKS_STOP; TASKS_CALIBRATEOFFSET; EVENTS_STARTED; EVENTS_END; EVENTS_DONE; EVENTS_RESULTDONE; EVENTS_CALIBRATEDONE; EVENTS_STOPPED; INTEN; INTENSET; INTENCLR; STATUS; ENABLE; RESOLUTION; OVERSAMPLE; SAMPLERATE; RESULT_PTR; RESULT_MAXCNT; RESULT_AMOUNT; CH_0_PSELP; CH_1_PSELP; CH_2_PSELP; CH_3_PSELP; CH_4_PSELP; CH_5_PSELP; CH_6_PSELP; CH_7_PSELP; CH_0_PSELN; CH_1_PSELN; CH_2_PSELN; CH_3_PSELN; CH_4_PSELN; CH_5_PSELN; CH_6_PSELN; CH_7_PSELN; CH_0_CONFIG; CH_1_CONFIG; CH_2_CONFIG; CH_3_CONFIG; CH_4_CONFIG; CH_5_CONFIG; CH_6_CONFIG; CH_7_CONFIG; CH_0_LIMIT; CH_1_LIMIT; CH_2_LIMIT; CH_3_LIMIT; CH_4_LIMIT; CH_5_LIMIT; CH_6_LIMIT; CH_7_LIMIT; EVENTS_CH_0_LIMITH; EVENTS_CH_1_LIMITH; EVENTS_CH_2_LIMITH; EVENTS_CH_3_LIMITH; EVENTS_CH_4_LIMITH; EVENTS_CH_5_LIMITH; EVENTS_CH_6_LIMITH; EVENTS_CH_7_LIMITH; EVENTS_CH_0_LIMITL; EVENTS_CH_1_LIMITL; EVENTS_CH_2_LIMITL; EVENTS_CH_3_LIMITL; EVENTS_CH_4_LIMITL; EVENTS_CH_5_LIMITL; EVENTS_CH_6_LIMITL; EVENTS_CH_7_LIMITL; } /// Timer/Counter 0 pub mod TIMER0 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 1 pub mod TIMER1 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 2 pub mod TIMER2 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Real time counter 0 pub mod RTC0 { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Temperature Sensor pub mod TEMP { TASKS_START; TASKS_STOP; EVENTS_DATARDY; INTENSET; INTENCLR; TEMP; A0; A1; A2; A3; A4; A5; B0; B1; B2; B3; B4; B5; T0; T1; T2; T3; T4; } /// Random Number Generator pub mod RNG { TASKS_START; TASKS_STOP; EVENTS_VALRDY; SHORTS; INTENSET; INTENCLR; CONFIG; VALUE; } /// AES ECB Mode Encryption pub mod ECB { TASKS_STARTECB; TASKS_STOPECB; EVENTS_ENDECB; EVENTS_ERRORECB; INTENSET; INTENCLR; ECBDATAPTR; } /// AES CCM Mode Encryption pub mod CCM { TASKS_KSGEN; TASKS_CRYPT; TASKS_STOP; EVENTS_ENDKSGEN; EVENTS_ENDCRYPT; EVENTS_ERROR; SHORTS; INTENSET; INTENCLR; MICSTATUS; ENABLE; MODE; CNFPTR; INPTR; OUTPTR; SCRATCHPTR; } /// Accelerated Address Resolver pub mod AAR { !TASKS_START; !TASKS_STOP; !EVENTS_END; !EVENTS_RESOLVED; !EVENTS_NOTRESOLVED; !INTENSET; !INTENCLR; !STATUS; !ENABLE; !NIRK; !IRKPTR; !ADDRPTR; !SCRATCHPTR; } /// Watchdog Timer pub mod WDT { TASKS_START; EVENTS_TIMEOUT; INTENSET; INTENCLR; RUNSTATUS; REQSTATUS; CRV; RREN; CONFIG; RR_0; RR_1; RR_2; RR_3; RR_4; RR_5; RR_6; RR_7; } /// Real time counter 1 pub mod RTC1 { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Quadrature Decoder pub mod QDEC { TASKS_START; TASKS_STOP; TASKS_READCLRACC; TASKS_RDCLRACC; TASKS_RDCLRDBL; EVENTS_SAMPLERDY; EVENTS_REPORTRDY; EVENTS_ACCOF; EVENTS_DBLRDY; EVENTS_STOPPED; SHORTS; INTENSET; INTENCLR; ENABLE; LEDPOL; SAMPLEPER; SAMPLE; REPORTPER; ACC; ACCREAD; DBFEN; LEDPRE; ACCDBL; ACCDBLREAD; PSEL_LED; PSEL_A; PSEL_B; } /// Comparator pub mod COMP { TASKS_START; TASKS_STOP; TASKS_SAMPLE; EVENTS_READY; EVENTS_DOWN; EVENTS_UP; EVENTS_CROSS; SHORTS; INTEN; INTENSET; INTENCLR; RESULT; ENABLE; PSEL; REFSEL; EXTREFSEL; TH; MODE; HYST; ISOURCE; } /// Low Power Comparator pub mod LPCOMP { !TASKS_START; !TASKS_STOP; !TASKS_SAMPLE; !EVENTS_READY; !EVENTS_DOWN; !EVENTS_UP; !EVENTS_CROSS; !SHORTS; !INTENSET; !INTENCLR; !RESULT; !ENABLE; !PSEL; !REFSEL; !EXTREFSEL; !HYST; ANADETECT; } /// Software interrupt 0 pub mod SWI0 { UNUSED; } /// Event Generator Unit 0 pub mod EGU0 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 1 pub mod SWI1 { UNUSED; } /// Event Generator Unit 1 pub mod EGU1 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 2 pub mod SWI2 { UNUSED; } /// Event Generator Unit 2 pub mod EGU2 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 3 pub mod SWI3 { UNUSED; } /// Event Generator Unit 3 pub mod EGU3 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 4 pub mod SWI4 { UNUSED; } /// Event Generator Unit 4 pub mod EGU4 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Software interrupt 5 pub mod SWI5 { UNUSED; } /// Event Generator Unit 5 pub mod EGU5 { !TASKS_TRIGGER_0; !TASKS_TRIGGER_1; !TASKS_TRIGGER_2; !TASKS_TRIGGER_3; !TASKS_TRIGGER_4; !TASKS_TRIGGER_5; !TASKS_TRIGGER_6; !TASKS_TRIGGER_7; !TASKS_TRIGGER_8; !TASKS_TRIGGER_9; !TASKS_TRIGGER_10; !TASKS_TRIGGER_11; !TASKS_TRIGGER_12; !TASKS_TRIGGER_13; !TASKS_TRIGGER_14; !TASKS_TRIGGER_15; EVENTS_TRIGGERED_0; EVENTS_TRIGGERED_1; EVENTS_TRIGGERED_2; EVENTS_TRIGGERED_3; EVENTS_TRIGGERED_4; EVENTS_TRIGGERED_5; EVENTS_TRIGGERED_6; EVENTS_TRIGGERED_7; EVENTS_TRIGGERED_8; EVENTS_TRIGGERED_9; EVENTS_TRIGGERED_10; EVENTS_TRIGGERED_11; EVENTS_TRIGGERED_12; EVENTS_TRIGGERED_13; EVENTS_TRIGGERED_14; EVENTS_TRIGGERED_15; INTEN; INTENSET; INTENCLR; } /// Timer/Counter 3 pub mod TIMER3 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Timer/Counter 4 pub mod TIMER4 { TASKS_START; TASKS_STOP; TASKS_COUNT; TASKS_CLEAR; TASKS_SHUTDOWN; TASKS_CAPTURE_0; TASKS_CAPTURE_1; TASKS_CAPTURE_2; TASKS_CAPTURE_3; TASKS_CAPTURE_4; TASKS_CAPTURE_5; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; EVENTS_COMPARE_4; EVENTS_COMPARE_5; SHORTS; INTENSET; INTENCLR; MODE; BITMODE; PRESCALER; CC_0; CC_1; CC_2; CC_3; CC_4; CC_5; } /// Pulse Width Modulation Unit 0 pub mod PWM0 { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse Density Modulation (Digital Microphone) Interface pub mod PDM { TASKS_START; TASKS_STOP; EVENTS_STARTED; EVENTS_STOPPED; EVENTS_END; INTEN; INTENSET; INTENCLR; ENABLE; PDMCLKCTRL; MODE; GAINL; GAINR; SAMPLE_PTR; SAMPLE_MAXCNT; PSEL_CLK; PSEL_DIN; } /// Non Volatile Memory Controller pub mod NVMC { READY; CONFIG; ERASEPAGE; !ERASEPCR1; ERASEALL; ERASEPCR0; ERASEUICR; ICACHECNF; IHIT; IMISS; } /// Programmable Peripheral Interconnect pub mod PPI { CHEN; CHENSET; CHENCLR; CHG_0; CHG_1; CHG_2; CHG_3; CHG_4; CHG_5; FORK_0_TEP; FORK_1_TEP; FORK_2_TEP; FORK_3_TEP; FORK_4_TEP; FORK_5_TEP; FORK_6_TEP; FORK_7_TEP; FORK_8_TEP; FORK_9_TEP; FORK_10_TEP; FORK_11_TEP; FORK_12_TEP; FORK_13_TEP; FORK_14_TEP; FORK_15_TEP; FORK_16_TEP; FORK_17_TEP; FORK_18_TEP; FORK_19_TEP; FORK_20_TEP; FORK_21_TEP; FORK_22_TEP; FORK_23_TEP; FORK_24_TEP; FORK_25_TEP; FORK_26_TEP; FORK_27_TEP; FORK_28_TEP; FORK_29_TEP; FORK_30_TEP; FORK_31_TEP; CH_0_EEP; CH_1_EEP; CH_2_EEP; CH_3_EEP; CH_4_EEP; CH_5_EEP; CH_6_EEP; CH_7_EEP; CH_8_EEP; CH_9_EEP; CH_10_EEP; CH_11_EEP; CH_12_EEP; CH_13_EEP; CH_14_EEP; CH_15_EEP; CH_16_EEP; CH_17_EEP; CH_18_EEP; CH_19_EEP; CH_0_TEP; CH_1_TEP; CH_2_TEP; CH_3_TEP; CH_4_TEP; CH_5_TEP; CH_6_TEP; CH_7_TEP; CH_8_TEP; CH_9_TEP; CH_10_TEP; CH_11_TEP; CH_12_TEP; CH_13_TEP; CH_14_TEP; CH_15_TEP; CH_16_TEP; CH_17_TEP; CH_18_TEP; CH_19_TEP; TASKS_CHG_0_EN; TASKS_CHG_1_EN; TASKS_CHG_2_EN; TASKS_CHG_3_EN; TASKS_CHG_4_EN; TASKS_CHG_5_EN; TASKS_CHG_0_DIS; TASKS_CHG_1_DIS; TASKS_CHG_2_DIS; TASKS_CHG_3_DIS; TASKS_CHG_4_DIS; TASKS_CHG_5_DIS; } /// Memory Watch Unit pub mod MWU { INTEN; INTENSET; INTENCLR; NMIEN; NMIENSET; NMIENCLR; REGIONEN; REGIONENSET; REGIONENCLR; PREGION_0_START; PREGION_1_START; PREGION_0_END; PREGION_1_END; PREGION_0_SUBS; PREGION_1_SUBS; REGION_0_START; REGION_1_START; REGION_2_START; REGION_3_START; REGION_0_END; REGION_1_END; REGION_2_END; REGION_3_END; PERREGION_0_SUBSTATWA; PERREGION_1_SUBSTATWA; PERREGION_0_SUBSTATRA; PERREGION_1_SUBSTATRA; EVENTS_PREGION_0_WA; EVENTS_PREGION_1_WA; EVENTS_PREGION_0_RA; EVENTS_PREGION_1_RA; EVENTS_REGION_0_WA; EVENTS_REGION_1_WA; EVENTS_REGION_2_WA; EVENTS_REGION_3_WA; EVENTS_REGION_0_RA; EVENTS_REGION_1_RA; EVENTS_REGION_2_RA; EVENTS_REGION_3_RA; } /// Pulse Width Modulation Unit 1 pub mod PWM1 { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Pulse Width Modulation Unit 2 pub mod PWM2 { TASKS_STOP; TASKS_SEQSTART_0; TASKS_SEQSTART_1; TASKS_NEXTSTEP; EVENTS_STOPPED; EVENTS_SEQSTARTED_0; EVENTS_SEQSTARTED_1; EVENTS_SEQEND_0; EVENTS_SEQEND_1; EVENTS_PWMPERIODEND; EVENTS_LOOPSDONE; SHORTS; INTEN; INTENSET; INTENCLR; ENABLE; MODE; COUNTERTOP; PRESCALER; DECODER; LOOP; PSEL_OUT_0; PSEL_OUT_1; PSEL_OUT_2; PSEL_OUT_3; SEQ_0_PTR; SEQ_1_PTR; SEQ_0_CNT; SEQ_1_CNT; SEQ_0_REFRESH; SEQ_1_REFRESH; SEQ_0_ENDDELAY; SEQ_1_ENDDELAY; } /// Serial Peripheral Interface Master with EasyDMA 2 pub mod SPIM2 { TASKS_START; TASKS_STOP; TASKS_SUSPEND; TASKS_RESUME; EVENTS_STOPPED; EVENTS_ENDRX; EVENTS_END; EVENTS_ENDTX; EVENTS_STARTED; SHORTS; INTENSET; INTENCLR; ENABLE; FREQUENCY; CONFIG; ORC; TXD_PTR; TXD_MAXCNT; TXD_AMOUNT; TXD_LIST; RXD_PTR; RXD_MAXCNT; RXD_AMOUNT; RXD_LIST; PSEL_SCK; PSEL_MOSI; PSEL_MISO; } /// SPI Slave 2 pub mod SPIS2 { !EVENTS_END; !EVENTS_ENDRX; !SHORTS; !INTENSET; !INTENCLR; !ENABLE; !CONFIG; !ORC; !TXD_PTR; !TXD_MAXCNT; !TXD_AMOUNT; !RXD_PTR; !RXD_MAXCNT; !RXD_AMOUNT; !PSEL_SCK; !PSEL_MISO; !PSEL_MOSI; TASKS_ACQUIRE; TASKS_RELEASE; EVENTS_ACQUIRED; SEMSTAT; STATUS; DEF; PSEL_CSN; } /// Serial Peripheral Interface 2 pub mod SPI2 { !INTENSET; !INTENCLR; !ENABLE; !FREQUENCY; !CONFIG; !PSEL_SCK; !PSEL_MOSI; !PSEL_MISO; EVENTS_READY; RXD; TXD; } /// Real time counter 2 pub mod RTC2 { TASKS_START; TASKS_STOP; TASKS_CLEAR; TASKS_TRIGOVRFLW; EVENTS_TICK; EVENTS_OVRFLW; EVENTS_COMPARE_0; EVENTS_COMPARE_1; EVENTS_COMPARE_2; EVENTS_COMPARE_3; INTENSET; INTENCLR; EVTEN; EVTENSET; EVTENCLR; COUNTER; PRESCALER; CC_0; CC_1; CC_2; CC_3; } /// Inter-IC Sound pub mod I2S { TASKS_START; TASKS_STOP; EVENTS_RXPTRUPD; EVENTS_STOPPED; EVENTS_TXPTRUPD; INTEN; INTENSET; INTENCLR; ENABLE; PSEL_MCK; PSEL_SCK; PSEL_LRCK; PSEL_SDIN; PSEL_SDOUT; RXTXD_MAXCNT; TXD_PTR; RXD_PTR; CONFIG_MODE; CONFIG_RXEN; CONFIG_TXEN; CONFIG_MCKEN; CONFIG_MCKFREQ; CONFIG_RATIO; CONFIG_SWIDTH; CONFIG_ALIGN; CONFIG_FORMAT; CONFIG_CHANNELS; } /// FPU pub mod FPU { UNUSED; } /// GPIO Port 1 pub mod P0 { OUT; OUTSET; OUTCLR; IN; DIR; DIRSET; DIRCLR; LATCH; DETECTMODE; PIN_CNF_0; PIN_CNF_1; PIN_CNF_2; PIN_CNF_3; PIN_CNF_4; PIN_CNF_5; PIN_CNF_6; PIN_CNF_7; PIN_CNF_8; PIN_CNF_9; PIN_CNF_10; PIN_CNF_11; PIN_CNF_12; PIN_CNF_13; PIN_CNF_14; PIN_CNF_15; PIN_CNF_16; PIN_CNF_17; PIN_CNF_18; PIN_CNF_19; PIN_CNF_20; PIN_CNF_21; PIN_CNF_22; PIN_CNF_23; PIN_CNF_24; PIN_CNF_25; PIN_CNF_26; PIN_CNF_27; PIN_CNF_28; PIN_CNF_29; PIN_CNF_30; PIN_CNF_31; } } => { ... }; }
Defines an index of nrf52 register tokens.