Trait drone_cortexm::thr::ThrNvic

pub trait ThrNvic: IntToken {
    pub fn enable_batch<F>(&self, f: F)
    where
        F: FnOnce(&mut NvicIser<Self::NvicBlock>),
    { ... }
    pub fn enable(&self, nvic_reg: &mut NvicIser<Self::NvicBlock>) { ... }
    pub fn enable_int(&self) { ... }
    pub fn enabled(&self) -> NvicIser<Self::NvicBlock> { ... }
    pub fn is_enabled(&self, nvic_reg: &NvicIser<Self::NvicBlock>) -> bool { ... }
    pub fn is_int_enabled(&self) -> bool { ... }
    pub fn disable_batch<F>(&self, f: F)
    where
        F: FnOnce(&mut NvicIcer<Self::NvicBlock>),
    { ... }
    pub fn disable(&self, nvic_reg: &mut NvicIcer<Self::NvicBlock>) { ... }
    pub fn disable_int(&self) { ... }
    pub fn set_pending_batch<F>(&self, f: F)
    where
        F: FnOnce(&mut NvicIspr<Self::NvicBlock>),
    { ... }
    pub fn set_pending(&self, nvic_reg: &mut NvicIspr<Self::NvicBlock>) { ... }
    pub fn set_pending_int(&self) { ... }
    pub fn clear_pending_batch<F>(&self, f: F)
    where
        F: FnOnce(&mut NvicIcpr<Self::NvicBlock>),
    { ... }
    pub fn clear_pending(&self, nvic_reg: &mut NvicIcpr<Self::NvicBlock>) { ... }
    pub fn clear_pending_int(&self) { ... }
    pub fn pending(&self) -> NvicIcpr<Self::NvicBlock> { ... }
    pub fn is_pending(&self, nvic_reg: &NvicIcpr<Self::NvicBlock>) -> bool { ... }
    pub fn is_int_pending(&self) -> bool { ... }
    pub fn active(&self) -> NvicIabr<Self::NvicBlock> { ... }
    pub fn is_active(&self, nvic_reg: &NvicIabr<Self::NvicBlock>) -> bool { ... }
    pub fn is_int_active(&self) -> bool { ... }
    pub fn priority(&self) -> u8 { ... }
    pub fn set_priority(&self, priority: u8) { ... }
}

NVIC methods for interrupt tokens.

Provided methods

pub fn enable_batch<F>(&self, f: F) where
    F: FnOnce(&mut NvicIser<Self::NvicBlock>), 

Enables multiple interrupts within the NVIC register.

pub fn enable(&self, nvic_reg: &mut NvicIser<Self::NvicBlock>)

Enables the interrupt.

pub fn enable_int(&self)

Enables the interrupt within the nvic_reg.

pub fn enabled(&self) -> NvicIser<Self::NvicBlock>

Returns the NVIC register of enabled states.

pub fn is_enabled(&self, nvic_reg: &NvicIser<Self::NvicBlock>) -> bool

Returns true if the interrupt is enabled.

pub fn is_int_enabled(&self) -> bool

Returns true if the interrupt is enabled within the nvic_reg.

pub fn disable_batch<F>(&self, f: F) where
    F: FnOnce(&mut NvicIcer<Self::NvicBlock>), 

Disables multiple interrupts within the NVIC register.

pub fn disable(&self, nvic_reg: &mut NvicIcer<Self::NvicBlock>)

Disables the interrupt.

pub fn disable_int(&self)

Disables the interrupt within the nvic_reg.

pub fn set_pending_batch<F>(&self, f: F) where
    F: FnOnce(&mut NvicIspr<Self::NvicBlock>), 

Sets multiple interrupts pending within the NVIC register.

pub fn set_pending(&self, nvic_reg: &mut NvicIspr<Self::NvicBlock>)

Sets the interrupt pending.

pub fn set_pending_int(&self)

Sets the interrupt pending within the nvic_reg.

pub fn clear_pending_batch<F>(&self, f: F) where
    F: FnOnce(&mut NvicIcpr<Self::NvicBlock>), 

Clears multiple interrupts pending state within the NVIC register.

pub fn clear_pending(&self, nvic_reg: &mut NvicIcpr<Self::NvicBlock>)

Clears the interrupt pending state.

pub fn clear_pending_int(&self)

Clears the interrupt pending state within the nvic_reg.

pub fn pending(&self) -> NvicIcpr<Self::NvicBlock>

Returns the NVIC register of pending states.

pub fn is_pending(&self, nvic_reg: &NvicIcpr<Self::NvicBlock>) -> bool

Returns true if the interrupt is pending.

pub fn is_int_pending(&self) -> bool

Returns true if the interrupt is pending within the nvic_reg.

pub fn active(&self) -> NvicIabr<Self::NvicBlock>

Returns the NVIC register of active states.

pub fn is_active(&self, nvic_reg: &NvicIabr<Self::NvicBlock>) -> bool

Returns true if the interrupt is active.

pub fn is_int_active(&self) -> bool

Returns true if the interrupt is active within the nvic_reg.

pub fn priority(&self) -> u8

Reads the priority of the interrupt.

pub fn set_priority(&self, priority: u8)

Writes the priority of the interrupt.

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Implementors

impl<T: IntToken> ThrNvic for T

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